積體電路之系統層級靜電放電暫態偵測電路設計

Abstract

隨者互補式金氧半導體(Complementary Metal-Oxide-Semiconductor, CMOS)積體電路(Integrated Circuits, IC)製程技術的演進，積體電路中的電晶體尺寸逐漸縮小，日益複雜的功能整合在相同積體電路之中，造成積體電路對靜電放電(Electrostatic Discharge, ESD)的耐受度下降，更容易使得在靜電放電的瞬間對積體電路產生破壞，所以靜電放電防護在微電子產品良率及可靠度上扮演相當重要的角色。 由於系統層級靜電放電測試規範(IEC 61000-4-2)之嚴格要求，越來越多的積體電路對系統層級靜電放電更為敏感，即使已經符合元件層級靜電放電(Component-Level ESD)規範之測試，依然無法達到系統層級靜電放電之相關要求。在系統層級靜電放電測試下，一個擁有積體電路的電子設備在接觸放電(Contact-Discharge)及空氣放電(Air-Discharge)測試模式中如欲達到“等級四”的標準需求，則此待測設備(Equipment under Test, EUT)必須通過高達±8kV(接觸放電模式)及±15kV(空氣放電模式)的靜電放電等級(ESD Level)需求。在此測試進行時，待測設備中的積體電路會遭受到由外部耦合(Coupling)至內部的靜電放電能量之影響，一旦此種由靜電放電所造成的暫態電壓耦合至積體電路的電源線(Power Line)上，便有可能引發電子設備不正常工作，甚至損毀。在傳統的防護方法中，多種不同的分離元件被應用於微電子產品之中，但是明顯增加了微電子產品的生產成本。因此，對於系統層級靜電放電防護而言，應用於金氧半導體製程的積體電路設計防護方法具有其重要性。 本論文首先於第二章與第三章提出了採用0.18-□m金氧半導體製程之二個系統層級靜電放電暫態偵測電路設計，經由相關模擬以及量測證實，此暫態偵測電路能夠偵測到系統層級靜電放電在電源線上所造成之暫態電壓，並且能夠送出轉態之邏輯訊號。相關的量測方式包括：暫態觸發閂鎖效應測試(Transient-Induced Latchup Test, TLU Test)、系統層級靜電放電測試(System-Level ESD Test)、電性快速脈衝測試(EFT Test)。 其次，暫態偵測電路對於偵測系統層級靜電放電引發之暫態電壓的偵測範圍將在第四章被研究討論，在此採用了多種不同的雜訊濾波器，藉由其對電源線上雜訊抑制的功能，配合暫態偵測電路做量測，證實雜訊濾波器可以改變暫態偵測電路在系統層級靜電放電測試下之偵測範圍。 最後，第五章提出了一個結合雜訊濾波器以及暫態偵測電路的四位元暫態轉數位之轉換器，此種轉換器可以成功的將系統層級靜電放電之電壓轉換為數位訊號輸出，因此能夠確切知道積體電路在系統層級靜電放電測試之下所遭受影響之程度，並期望未來能夠藉由此數位訊號配合軟體以及韌體之設計，對於電子系統做出不同程度的應用，使得具有積體電路的微電子產品能夠通過系統層級靜電放電相關規範之要求。

As the improvement of semiconductor process and technology, the device size of CMOS ICs has been scaled down and more complicated functions are integrated into a single chip. The potential destructive nature of ESD in CMOS ICs becomes serious and the design of ESD protection circuits becomes more challenging in scaled-down CMOS process. Therefore ESD protection has become an important reliability issue in CMOS IC products. System-level ESD is an increasingly important reliability issue in CMOS IC products. It has been also reported that reliability issues still exist in CMOS ICs under system-level ESD tests, even though they have passed component-level ESD specifications. In order to meet high electromagnetic compatibility (EMC) regulations, the microelectronic products are required to evaluate system performance under reliability test standard of system-level ESD tests. In the system-level ESD test standard of IEC 61000-4-2, the microelectronic products are required to sustain the ESD voltage of ±8kV (±15kV) under contact-discharge (air-discharge) test mode to achieve the immunity requirement of “level 4”. The experimental results have confirmed that the power and ground lines of microelectronic products no longer maintain the normal operating voltage under system-level ESD tests, but underdamped sinusoidal waveforms instead. Furthermore, the transient noise under system-level ESD tests can cause system into locked state, system frozed state, transient-induced latch-up, or even hardware damage. In traditional solutions, extra discrete components are added on PCB to suppress system-level ESD events in microelectronic products. Therefore, the chip-level solutions to meet high system-level ESD specification for microelectronic products are strongly requested by IC industry. In chapter 2, two transient detection circuits have been designed and investigated to detect the fast electrical transients on the power line (VDD) and ground line (VSS) under system-level ESD tests. In chapter 3, the proposed on-chip transient detection circuits have been fabricated in a 0.18-μm CMOS process with 3.3-V devices. The circuit performance of the circuits has been evaluated by transient induced latchup (TLU) tests, system-level ESD tests, and EFT tests. It has been confirmed that the transient detection circuits can detect and memorize the occurrence of the positive (negative) fast electrical transients on the power and ground lines of CMOS ICs. Evaluation on the board-level noise filter network to reduce the ESD energy coupling into the DUT under system-level ESD tests is investigated in chapter 4. Different types of board-level noise filters, including capacitor filter, LC-like (2nd-order) filter, π-section (3rd-order) filter, etc., have been evaluated to change the detection range of the proposed on-chip transient detection circuits. In chapter 5, a novel on-chip transient-to-digital converter composed of four transient detection circuits and four different RC filters has been successfully designed and verified in a 0.18-μm CMOS process with 3.3-V devices. The output thermometer digital codes of the proposed on-chip transient-to-digital converter correspond to different positive/negative ESD voltages under system-level ESD tests. These output digital codes can be used as the firmware index to execute different auto-recovery procedures in microelectronic systems. Therefore, the system with auto-detection function can detect the transient noise and then automatically reset itself to achieve the “Class B” specification defined in the IEC 61000-4-2 standard.