用於IEEE 802.116d及IEEE 802.11a/g之CORDIC 多模同步電路設計

Abstract

本論文提出一個適用於IEEE802.11a/g 及IEEE802.16d 之多模同步電路。所提出的同步電路中可以細分為訊框偵測，分數載波頻率漂移估測，整數載波頻率漂移估測及符元邊界偵測。在訊框偵測中，本論文提出一個修改過的絕對值近似方法.這個方法可以使近似的誤差降低2~3倍。在分數載波頻率漂移估測中，本論文提出一個修改過的座標旋轉數位計算機電路。相對於傳統的方法，這個座標旋轉數位計算機電路可以使得硬體複雜度降低46%。在整數載波頻率漂移中，本論文使用一個簡化的匹配濾波器以降低非共用電路所佔的比例。系統模擬是建構在MathWorks 的MATLAB 平台上。整個電路架構也已經在Verilog 語言下實現出來。在UMC 0.18微米的製程環境下使用新思科技的Design Compiler所合成出來的結果顯示，多模同步電路的總gate count 大約是124k。

In this thesis, a multimode synchronization circuit ispresented. It consists of frame etection, fractional carrier frequency offset estimation, and integral carrier frequency ffset estimation and symbol boundary detection. In frame detection, a modified bsolute value approximation circuit (AVAC) is provided. It improves accuracy 2~3 times the accuracy of traditional method. In fractional carrier frequency offset estimation, a modified CORDIC circuit is proposed. The hardware reduction is at least 46% comparing to conventional method. In integral carrier frequency offset estimation,a reduced match filter is used. System simulation has done in Matlab. The architecture has been implemented in Verilog. By synthesizing to UMC 0.18um CMOS standard cell technology library with Synopsys Design Compiler,the overall gate count is about 124k