適用於3GPP-LTE規格的可重組渦輪解碼器之研究

Abstract

本論文提出了一個支援全模式且可重組的渦輪解碼器。我們提出的解碼器可以支援所有定義在3GPP-LTE 規格裡的編碼長度。而為了提高傳輸速度，遞迴解碼的平行架構更是受到關注。具有contention-free 特性的二次多項式交錯器也被應用在渦輪解碼器的平行架構中。Max-Log MAP 演算法也被採用，可使在極小的效能損失下有效的減低硬體複雜度。此外，可重組的1/2/4/8-MAP 解碼器設計也被提出，此設計可使在解碼過程中，根據所需的效能或傳輸速度，提供一個解碼器可重組的功能。而依據二次多項式交錯器的特性，一個稱為residue-only interleaver 的方法可被用來減少記憶體的使用量。 根據在90nm製程下的實驗結果，在8 次迴圈的解碼模式下可以達到130Mb/s的傳輸速度，晶片面積是2.10mm2。此外，在0.9V的供應電壓，277MHz的操作頻率且編碼長度6144 下，功率消耗經量測過後為149.03mW。

In this thesis, a fully compliant and reconfigurable turbo decoder is presented to support all block lengths specified in 3GPP-LTE system. The contention-free quadratic permutation polynomial (QPP) interleaver is also introduced for parallel architecture of turbo codes. The parallel processing of iterative decoding is of interest for throughput increasing. The Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. Moreover, the reconfigurable 1/2/4/8-MAP decoders is proposed to decode the received codewords based on performance or throughput expected in different conditions. Based on QPP characteristic, the residue-only interleaver is adopted to reduce the memory storage. After implementation in a 90-nm 1P9M technology, the 130Mb/s data rate with 8 decoding iterations can be achieved in the 2.10 mm2 core area containing 602K gates. According to the post-layout simulation, the power consumption is 149.03mW worked at supply voltage 0.9V and clock rate 277MHz with block length 6144.