一種應用於連續近似式類比數位轉換器之數位校正方法

Abstract

傳統SAR ADC 的解析度主要受限於製程製作出的電容比例是否準確。 本論文提出一種適用於SAR ADC 的新穎校正方式。對於一個由已知比例關 係之方式所構成的待校電容陣列，我們可以使用此演算法去找出該陣列中各 個電容因製程變異而產生的誤差量，並將之數位化後儲存。然後，在SAR ADC 進行轉換時計算出每一輸出碼的誤差量再以數位方式修正，如此便可 提升該SAR ADC 的解析度。

由於此校正法採用全數位方式校正，因此具有低功耗且不容易受製程變 異或其他環境因素影響的優點。此外，所提出的校正演算法，不論各待校電 容的誤差量為正或負，在電路實現上僅需一個單向的類比參考電壓，就可以 找出各電容的數位誤差值。相較於文獻上其他需要兩個對稱參考電壓的校正 方式，成本更低也更具實用性。其所需的額外硬體除少數類比開關與電容 外，皆為數位電路，因此硬體成本很低且非常容易移植到先進製程。

我們使用TSMC 0.18μm 1P6M CMOS 製程設計並實現一具校正功能的 1-V，12-bit SAR ADC 之晶片，來驗證此校正法是否有效。實際測量顯示， 對於同一個晶片，開啟校正功能的SAR ADC 可以操作在更快的時脈頻率， 並且擁有更寬的有效頻寬；此晶片之DNL 與INL 在經過校正後，分別由 -1~+18 個LSB 與-8~+18 個LSB，大幅降至-1~+9 個LSB 與-6~+9 個LSB； 且在同樣的輸入信號下，開啟校正功能後其SNDR 最多有5dB 的改善，換 言之經校正後約可提升1 個有效位元，且在1-V 的電源電壓下其耗能僅 20μW。

It is the mismatched capacitors due to process variation that mainly limit the resolution of conventional SAR ADCs. To address this issue, this thesis proposes a novel calibration scheme for SAR ADCs. The proposed calibration scheme first estimates the ratio errors of the capacitors under calibration in the weighted capacitive array. Then, the errors will be digitized and stored. During the normal conversion of SAR ADCs, the corresponding error code of every ADC’s output will be calculated according to the stored error codes. Finally, the error code will be compensated in digital domain. With the proposed calibration scheme, the resolution of the SAR ADC can be enhanced.

The hardware overhead consists of several capacitors and a few of switches in addition to the digital function blocks. Since the proposed calibration scheme estimates and calibrates the errors digitally, it is very robust, low-power, and can be easily ported to advanced technologies. In practical implementation, only one reference voltage is necessary no matter the capacitor errors are positive or negative. Comparing with the state-of-the-art calibration schemes which require precisely symmetric dual reference voltages to handle the signed errors, the proposed calibration scheme is more practical and low-cost.

We implemented a 1-V SAR ADC with the proposed calibration scheme in TSMC 0.18μm 1P6M CMOS process. Measurement results show that the SAR ADC can operate faster and has a wider effective resolution bandwidth after calibration. The DNL and INL values are enhanced from -1~+18 LSB and -8~+18 LSB to -1~+9 LSB and -6~+9 LSB after calibration. With the same input, the SNDR of the ADC can have up to 5dB improvement after calibration. It corresponds to around an additional effective number of bit (ENOB). The ADC consumes less than 20μW at 1-V.