應用半均等量化及改良式延遲時間補償連續時間之三角積分調變器

Abstract

隨著無線通訊的蓬勃發展，應用於無線通訊中的類比數位轉換器也受到更多的矚目。在所有的類比數位轉換器的架構中，三角積分 ( Delta-sigma ) 類比數位轉換器優於快閃 ( Flash ) 和導管式 ( Pipeline ) 類比數位轉換器的地方，在於擁有較佳的頻寬和解析度的經濟效益。近年來，由於有著更低的功率消耗及較大的訊號頻寬，連續時間三角積分類比數位轉換器比起離散時間三角積分類比數位轉換器更為廣泛應用於無線通訊中。 在此篇論文中，我們著重於連續時間三角積分調變器的設計概念，且實現一1 MHz訊號頻寬，並具有60 dB動態範圍 ( Dynamic Range ) 及最大訊號雜訊失真比 ( SNDR ) 為59.6 dB的電路，此電路使用電阻取代原先轉導當作零點轉移的功用，以節省面積和功率。此外，我們也提出另一架構，此電路具有2MHz的訊號頻寬及最大訊號雜訊失真比63 dB且使用改良式延遲時間補償及半均等量化的技巧來節省面積和功率。 晶片分別以台積電180奈米互補式金氧半導體製程及130奈米互補式金氧半導體製程所製造。量測結果顯示第一顆晶片操作在100 MHz取樣頻率下，消耗13.7 mW的功率在1.8 V的供應電壓下。模擬結果顯示另一顆晶片操作在62.5 MHz取樣頻率下，消耗10 mW的功率在1.2 V的供應電壓下。

With the growth of wireless communication, there has been more focus on the analog-to-digital converter (ADC) for wireless applications. Among all of ADCs, delta-sigma converters are preferable over flash and pipeline converters because they offer the most economic bandwidth and accuracy trade-off. Recently, continuous-time delta-sigma ADCs get growing interests in wireless applications for their lower power consumption and wider bandwidth as compared with the discrete-time counterparts. In this thesis, it focuses on the design procedure of the continuous-time delta-sigma modulator and the first chip is presented to achieve 60 dB dynamic range and 59.6 dB SNDR within a 1MHz signal bandwidth. This work replaces the transconductor with resistors as the function of zero shifts to save chip area and power consumption. Besides, we also show the other architecture to achieve 63 dB SNDR within a 2MHz signal bandwidth and this work uses the techniques of improved zero-order loop compensation and semi-uniform quantization to save chip area and power consumption. The first chip has been fabricated by TSMC 180 nm CMOS process and the other has been fabricated by TSMC 130 nm CMOS process. The test results show that the first work consumes 13.7 mW with 100 MHz sample rate in 1.8 V supply voltage. The simulation results show that the other work consumes 10 mW with 62.5 MHz sample rate in 1.2 V supply voltage.