針對溫度及電壓變異所做之Logical Effort Model之延伸

Abstract

在積體電路設計中，電路效能的估計與電路最佳化設計是兩個最需要被重視的課題。”Logical Effort Delay Model”是一個可讓電路設計者以簡便的手算方式快速估計電路延遲並完成初步電路最佳化的方法。但是在已發表的各項關於logical effort model的改進或延伸的研究中，並沒有提出一個可適當處理製程、電壓或溫度變異的方法，而這些變異卻可能造成嚴重的錯誤估計。根據在90奈米製程下所得到的模擬結果，電路的延遲時間在溫度由0°C升高到125°C時會增加21%，而當供應電壓由1V降到0.5V時則會提高到原先的兩倍。因此，本論文對原始的logical effort g提出一個簡單的線性方式的延伸：1/g = (mtt+bt)VDD+C，使其能適用於溫度t及供應電壓VDD的變異，並利用其線性特性使設計者能便於計算，在CAD tool上的應用也較易於整合。本論文中所提出的logical effort model extension可讓電路設計者能在不同的溫度及電壓條件下，正確的估計整體電路的效能並完成電路最佳化設計。更進一步來說，在一個晶片中的各個區塊都可依其不同的溫度及電壓條件，各自完成最佳化的設計，此優點能使整體電路的效能得到更好的提升。經過驗證後可確認本論文所提出的延伸模型能達到大約90%的準確率。

In the integrated circuits design, performance estimation and circuit optimization are two of the most important issues. The method of “Logical Effort Delay Model” allows designers to quickly estimate delay time and optimize logic paths, but the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results in 90nm process, delay time increases 21% while temperature increasing from 0°C to 125°C. In the mean time, delay time increases 2X while supply voltage decreasing from 1V to 0.5V. Thus a simple linear extension of logical effort g, 1/g = (mtt+bt)VDD+C, supporting for temperature t and supply voltage V¬DD variations is presented. The linear characteristic is convenient for designers to calculate and the integration of proposed model and CAD tools is easier. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. Furthermore, each functional block on a chip can be optimized under different PVT conditions through this simple model. After validation, the accuracy of this new extended logical effort model can achieve about 90%.