應用於高速序列資料之表面聲波式半速率時脈回復電路

Abstract

本論文將利用TSMC 0.18um製程實現Stratum 3下之1.244Gb/s時脈回復電路並應用於OC-24中，在振盪器設計則採用低相位雜訊的表面聲波振盪器，完成一在OC-24光纖網路中運行之1.244Gb/s時脈資料回復電路。其中低通濾波器與表面聲波共振腔為接於IC外，迴路頻寬約在1KHz附近，相位偏移器將使用於表面聲波振盪器分兩部分討論，π 型相位偏移器外接與積體化於IC中，藉由MATLAB與HSPICE的模擬，本論文成功將表面聲波振盪器與時脈回復電路相互結合，並量測其在上鎖時得到回復時脈1.024ps(相位偏移器外接)與0.88ps(相位偏移器積體化)，在功率損耗上為30mW與143mW。

The purpose of this thesis is to implement a clock and data recovery (CDR) for Stratum 3. The bit rate is 1.244Gb/s for OC-24 by using TSMC 0.18um CMOS process. The voltage controlled SAW Oscillator (VCSO) is designed for low phase noise application. The low pass loop filter and SAW resonator are external connected. The loop bandwidth is around 1KHz. The necessitate phase shift in VCSO is describe in two parts. The first is external connected π network and the other is internally integrated. The MATLAB and HSPICE are used for behavior and circuit level simulation, respectively. The VCSO is successfully combined into CDR. The measured RMS jitter of retime clock is 1.024ps and 0.88ps for external and integrated phase shifter, respectively. The power consumptions are 30mW and 143mW.