應用於語音之三階三角積分數位類比轉換器

Abstract

近年來因為語音產品的蓬勃發展，如MP3隨聲聽等等，使得語音系統數位類比轉換器成為一個重要的目標。而對於用電池運作的語音系統有幾個問題是我們必須注意的。因為功率消耗會影響電池的壽命，所以必須把功率消耗設計的越小越好。另外，為了達到多媒體產品的品質需求，此數位類比轉換器必須達到約16位元的高解析度。

三角積分數位類比轉換器(Delta-Sigma D/A converter)是一種廣泛運用的技術，它能夠達到高解析度、降低數位電路部份的操作速度、能夠緩和頻帶外(out-of-band)濾波器的需求以及提高對時脈抖動(clock jitter)的免疫力。使用直接電荷轉換的切換式電阻電容技術可以減少kT/C雜訊和元件不匹配的影響而不增加功率消耗，並且比直接電荷轉換切換式電容技術擁有較少的失真。資料加權平均的演算法可以抑制電容之間的不匹配所造成的非線性度。

在此研究中我們將介紹一個15等級量化、三階的三角積分數位類比轉換器，取樣頻率是44.1千赫茲，輸入訊號為24位元，因為超取樣倍率為64倍，所以主要時脈操作在2.8224百萬赫茲，本次設計的晶片是由晶片中心(CIC)提供的台積電(tsmc)標準0.18微米製程中實現。在1.8伏特的供應電壓下可達87分貝的動態範圍，並且消耗8.25毫瓦特。

Audio digital-to-analog converters (DAC) have played an important role recently with the rapid growth of the cellular phone and portable audio devices. There are some main issues for a battery-operated audio system. Power dissipation affects the battery life, so it must be as low as possible. A high resolution of about 16bits is required for the DAC to meet the quality of the media.

The delta-sigma D/A converters have been used extensively. It can achieve high resolution, reduce digital circuit speed, relax the requirements of the out-of-band filter, and enhance immunity to clock jitter. Using the direct charge transfer switched-RC (DCT-SRC) technique in the multi-bit reconstruction DAC can reduce kT/C noise and element mismatch without increasing power dissipation. And this kind of DCT-SRC DAC has smaller distortion than direct charge transfer switch capacitor DAC (DCT-SCDAC). The data weighted averaging algorithm restrains nonlinearity caused by the mismatch of capacitors.

A 15-level quantization, third-order delta-sigma DAC is presented. Its sampling rate is 44.1 kHz with 24-bit input. The main clock is 2.8224 MHz because of the 64X oversampling ratio. This DAC implemented in a TSMC 0.18um CMOS process achieved 87dB dynamic range (DR), while consuming 8.25mW from a 1.8V supply.