A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC

doi:10.1109/JSSC.2007.905237

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DC 欄位	值	語言
dc.contributor.author	Hong, Hao-Chiao	en_US
dc.contributor.author	Lee, Guo-Ming	en_US
dc.date.accessioned	2014-12-08T15:05:24Z	-
dc.date.available	2014-12-08T15:05:24Z	-
dc.date.issued	2007-10-01	en_US
dc.identifier.issn	0018-9200	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/JSSC.2007.905237	en_US
dc.identifier.uri	http://hdl.handle.net/11536/3941	-
dc.description.abstract	An 8-bit successive approximation (SA) analog-to-digital converter (ADC) in 0.18 mu m CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 mu W in the test, corresponding to a figure of merit of 65 fJ/conversion-step.	en_US
dc.language.iso	en_US	en_US
dc.subject	ADC	en_US
dc.subject	energy efficient	en_US
dc.subject	low power	en_US
dc.subject	low supply voltage	en_US
dc.subject	mu W design	en_US
dc.subject	successive approximation	en_US
dc.title	A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC	en_US
dc.type	Article; Proceedings Paper	en_US
dc.identifier.doi	10.1109/JSSC.2007.905237	en_US
dc.identifier.journal	IEEE JOURNAL OF SOLID-STATE CIRCUITS	en_US
dc.citation.volume	42	en_US
dc.citation.issue	10	en_US
dc.citation.spage	2161	en_US
dc.citation.epage	2168	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:000249959300011	-
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