環繞式閘極多晶矽奈米線薄膜電晶體之特性

Abstract

本研究以側壁Spacer奈米線技術製作出環繞式閘極多晶矽薄膜電晶體，經過24小時退火的多晶矽奈米線，將其下面的BOX氧化層濕式蝕刻移除後，使奈米線呈懸梁臂的懸空狀態，再將薄氧化層沉積上去當閘極絕緣層，之後蓋上N+多晶矽薄膜，此層須將整個空隙填滿，包住整個通道，來提升閘極對通道的控制能力，改善短通道效應。元件完成後，經過氨電漿處理，發現它整個電性有非常明顯的改善，包括極高驅動電流，低次臨界擺幅(Subthreshold Swing)達到114 mV/dec、載子遷移率亦獲改善、幾乎零汲極引發位能障下降(DIBL)、高開關電流比(On-Off Current Ratio)>108、並有效抑止由於碰撞游離現象所造成的Kink效應。另外研究發現多通道的薄膜電晶體，有較低的臨界電壓，陡峭的次臨界斜率(107 mV/dec)，高電流開關比>109，但閘極引發汲極漏電流(GIDL)變得明顯。 此三維結構電晶體，藉由增加閘極對通道的控制面積，使得漏電得以控制，抑止短通道效應，元件特性比傳統的平面電晶體、雙閘極及三閘極還要好。由於多晶矽薄膜電晶體受限於晶粒邊界缺陷(Grain Boundary Traps)的問題，使得載子遷移率很低，開關電流比很難進一步提升，因此我們將通道四周包住，來提升閘極控制能力。再經過電漿處理，降低介面態(Interface State)與通道中晶粒邊界的缺陷密度，使元件有非常優越的特性，其改善的幅度遠大於其他團隊。

This thesis successfully demonstrated gate-all-around polycrystalline silicon (poly-Si) thin film transistor with side-wall spacer nanowire technique. The poly-Si nanowire after solid phase crystallization for 24 hours was released to suspension from buried oxide by using wet etching process in DHF solution. The released suspending nanowire was followed by a 20-nm TEOS deposition as gate oxide. Subsequently, a 200-nm-thick in situ n+ doped poly-Si layer was deposited and patterned to form a gate electrode. The channel about 70-nm-width was wrapped around by gate oxide and poly-Si gate. This gate-all-around structure exhibits superior channel controllability and immunity of short channel effects (SCEs). After the device fabricated, it was passivated by NH3 plasma treatment for 1 hour at 300℃. The device performance was improved after NH3 plasma treatment, including a high driving current, a steep subthreshold swing(114 mV/dec), a better mobility, near free of DIBL, a high on/off current ratio(>108), and suppression of kink effect induces by ion impacted ionization. In addition, the multiple channel nanowire TFTs have a lower threshold voltage, a steeper subthreshold swing(107 mV/dec), a higher on/off current ratio(>109), but gate induce drain leakage was serious than dual-channel device. In this 3-D structure, the increase of gate area over channel to suppress SCEs and leakage current were accomplished. The device shows excellent performance than conventional planar transistor, double gate fin-FET, and tri-gate fin-FET. Due to the poly-Si TFTs were limited by the defects of grain boundary, the carrier mobility and on/off ratio are difficult to enhance, GAA structure was adopted to overcome these limitations. The trap state density of grain boundaries can be further reduced after NH3 plasma passivation.