ARM指令集架構應用程式之靜態二進位轉譯及最佳化

Abstract

二進位碼的轉譯經常被用於將現有的程式移轉到新開發的指令集平台上。這篇論文裡將探討一個靜態二進位碼轉譯器，此轉譯器能將ARM指令集架構的二進位碼轉譯成類MIPS指令集架構的二進位碼，這個類MIPS指令集架構是專為嵌入式系統設計的新架構。此靜態轉譯器的功能包含基礎指令集架構轉換，以及以減少執行指令數為目標的最佳化。由於ARM指令集架構是一個條件式執行的指令集架構，在轉譯的過程中需要特別處理條件式執行的指令，也因此轉譯器對於條件式執行亦須提供最佳化。在經過各種對條件式執行的最佳化後，在我們用來評估效能的EEMBC程式集中，相對於被轉譯的ARM二進位碼，經由轉譯得到的二進位碼只需要額外執行35%的指令

Binary translation is often used in migrating legacy binaries to new architecture-based platforms. This thesis describes a static binary translator which translates ARM binaries to a MIPS-like architecture designed for embedded systems. The static translator handles basic architecture translations and performs optimizations to minimize instruction overhead. The conditional execution feature in the ARM architecture requires special attention on binary translation and optimization. With several optimizations to minimize condition updates and checks, the translated code from ARM to our target architecture increases the instruction path length by only 35% on the EEMBC benchmark.