建構新型Petri Nets模式與其應用

Abstract

本論文利用Petri nets可撓性，建構出Logical Petri nets 和 Boolean Petri nets，分別應用到電子領域中的積體電路測試(IC testing)與電機領域中的階梯圖(ladder diagram)測試、診斷和設計領域。 積體電路測試中，Logical Petri nets 是根據真值表(true table)之臨界值(critical value)所建構而成，具有布林代數(Boolean algorithm)和collapsing fault性質，使Petri nets具有清晰物理觀念。本文所提出前進演算法(forward algorithm)與後退演算法(backward algorithm)，即為了在組合電路(combinational circuit) 中，求得測試圖樣(test pattern)、故障點位置(site of fault) 和激發邏輯值(firing logic value)。 在階梯圖上，提出Boolean Petri nets (BPNs)建構的抽象模式(abstract model)，可直接從BPNs 的transition 時序，產生測試事件序列(test event sequence)和提供製作出客製積體電路(application- specific integrated circuits)。 此外，在設計可程式控制器方面，也可依系統規格直接建構BPNs抽象模式或利用IDEF0建構支援BPNs抽象模式可完成達到診斷、測試和控制器實現。最後經由一郵票打印程序(stamping process)提供一階梯邏輯圖設計、測試和實現，證實所提出方法有用的，另由與simplified Petri net controller (SPNC) 比較，證實BPNs是一簡潔模式。

Due to the flexibility of Petri nets (PNs) and their ability to construct various types of clear, readable and suitable plane models, PNs have been recently employed in industrial applications. In this thesis, a Logic Petri nets (LPNs) and a Boolean Petri nets (BPNs) were applied to test, diagnose, and design ladder diagrams (LDs) and to test integrated circuits (ICs). In IC tests, the proposed LPNs model possesses the properties of a Boolean algorithm including collapsing fault and clear physical concepts because the LPNs model was constructed according to the critical truth table of combinatorial circuits. To solve generated test patterns and determine fired logical values at the site of fault in combinational circuits, the proposed approach contains a site of fault and fired logical value reasoning algorithm and a test pattern generation reasoning algorithm. In existing LDs, the proposed BPNs was used to construct an abstract model that can directly generate test events from the transition sequence of the BPNs and can support the implementation of application-specific integrated circuits (ASIC). Moreover, in the design of programmable logic controllers (PLCs), the proposed abstract BPNs model can be constructed according to the specifications of the system or by employing the integration definition for function modeling (IDEF0). The abstract model developed in this thesis can directly generate a testing event sequence for PLC testing and diagnosing. Finally, an example of a stamping process is provided to illustrate the design, implementation, testing and troubleshooting process. Comparison of the basic elements (i.e., number of places, transitions, and arcs) of simplified Petri net controller (SPNC) (Lee, 2004) and BPNs are also given to demonstrate the usefulness of this approach.