應用於多核心系統晶片之節能晶內資料傳輸－以記憶儲存為重心

Abstract

隨著人們對於無所不在的無線高速資料傳輸多媒體影音需求逐年增加，多核心系統晶片要能有效地提供大量的資料運算、資料傳輸以及資料儲存才有辦法達到未來的系統需求。在本論文中，我們提出了適合於異質多核心系統晶片之晶內資料傳輸平台－以記憶儲存為重心之節能晶內資料傳輸平台，此平台由兩部分構成，分別為以記憶體為重心之晶內連線網路(memory-centric on-chip interconnection network)以及隨隨記憶體子系統(on-demand memory sub-system)。此平台提供足夠的資料傳輸頻寬、記憶體存取頻寬以及記憶儲容量，並將其應用在無線影像娛樂系統上。 以記憶體為重心之晶內連線網路提供微架構及構成要素給晶內資料傳輸平台，構成要素包括了路由器(router)、連接導線(link wires)及網路介面(network interface)。在連接導線部分，我們提出了具能源效應及可靠度頻道設計，利用自我修正節能編碼及自我補償電壓調整技術，能有效地減少導線間的耦合效應，並且提供頻道錯誤更正及電壓調整機制。在路由器方面，我們設計了兩階層先進先出資料暫存器，藉由提升集中式資料暫存器的使用率及降低線頭阻塞來提升晶內網路效能。為了更進一步的提升網路效能，我們也提出了具堵塞感知之適應性路由演算法，藉由偵測路由器附近的資料傳輸情況，可以避開雍塞的路線。此外，我們提出了具能源效益的路由表設計給晶內連線網路及IPv6使用，此路由表是由高速且低功率三元定址記憶(TCAM)體陣列構成，其中包含了互斥或邏輯閘的條件式維持器、蝴蝶式比較線連接、階層式搜尋線及電源截段技術。 隨選記憶體子系統負責有效地管理異質多核心系統晶片中多執行程序的記憶體存取，讓系統達到最佳的記憶體使用率。在所提出的隨選記憶體子系統中，主要包含了私有式記憶體管理器以及集中式記憶體管理器。在私有式記憶體管理器中，主要是負責控制第一層快取(L1 cache)存取；此外，我們也提出了一個借取機制，此機制可以動態地分配快取中的記憶體資源給晶內網路封包的暫存使用，以減少處理單元暫停的情況。而在集中式記憶體管理器中，主要是負責管理第二層快取(L2 cache)及外部記憶體之資料存取，利用所提出的適應性快取控制機制，我們可以根據不同處理單元的記憶體存取需求，動態地分配所需記憶體資源。此外，在集中式記憶體管理器中也建構了一個外部記憶體存取介面來有效地存取晶片外的動態記憶體(DRAM)。另外，針對應用於無線影像娛樂系統上的可階式視訊編碼(scalable video coding)，我們提出了跨層間預取資料（inter-layer pre-fetch）機制和有效率的動態記憶體位址轉換器來減少快取記憶體的失誤率以及記憶體的能源消耗。

With increasing demands on ubiquitous wireless high-data-rate multimedia services, it is critical to have efficient capabilities of the data processing, data communication and data storage to sustain the growth in multi-core system-on-chips (SoCs). In this dissertation, an energy-efficient memory-centric on-chip data communication platform, consisting of a memory-centric on-chip interconnection network (OCIN) and an on-demand memory sub-system, is proposed to provide enough data communication bandwidth, memory bandwidth and memory capacity for heterogeneous multi-core SoCs in wireless video entertainment systems. The memory-centric OCIN provides the micro-architecture and building blocks, including routers, link wires and network interfaces (NIs), for the on-chip data communication platform. Therefore, an energy-efficient and reliable channel desgn is presented via a self-corrected green coding scheme and a self-celibrated voltage scaling technique to reduce the couping effects of link wires and provide the error correction and voltage scaling mechanisms. Conseuqently, a two-level FIFO buffer router is proposed to enhance the on-chip network performance by increasing the utility of the centralized buffer and reducing the head-of-line blocking problems. Accordingly, an adaptive congestion-aware routing algorithm is also proposed to further increase the performance of mesh networks by detecting the traffic around a routing node. Moreover, energy-efficient routing tables are presented for OCINs and IPv6 applications via the high-performance and low-power ternary content addressable memory (TCAM), which is desinged by noise-tolerant XOR-based conditional keepers, butterfly match-lines, don’t-care-based hierarchical search-lines and don’t-care-based power gating. The on-demand memory sub-system is presented to efficiently manage memory accesses of multi tasks in heterogeneous multi-core SoCs via private memory management units (p-MMUs) and a centralized MMU (c-MMU). The p-MMUs control data accesses of L1 caches and dynamically allocate memory resources for network data buffering to reduce the stall of processor elements (PEs) based on the proposed borrowing mechanism. Furthermore, the c-MMU manages centralized on-chip memories (L2 cache) and off-chip memories. For different memory requirements of the PEs in multi tasks, adaptive memory resource allocation is realized to increasing the ovaerall performance using the proposed adaptive cache control. Additionally, an external memory interface (EMI) is develpoed in the c-MMU to access the off-chip DRAM efficiently. Furthermore, an inter-layer pre-fetch mechanism and an efficient address translator are proposed to reduce both the cache miss rate and memory energy consumption for scalable video coding (SVC) in the wireless video entertainment system.