單級並聯型升壓返馳式轉換器

Abstract

無論單級式或兩級式交直流轉換器，均有部份電能會重覆處理或循環。因此，本論文應用了並聯式功因校正的概念，提出了一種嶄新的單級並聯式功率因數校正設計。此設計係利用升壓-返馳半級﹙包括升壓單元和返馳單元﹚產生兩條並聯電能處理路徑。主要的輸入功率經反馳單元轉換後即輸出至負載，而剩餘的功率經升壓單元處理，再儲入大型電容，然後被直流-直流半級取出作為輸出功率調節。理論分析證實，只要升壓單元和反馳單元運轉於非連續模式，且工作週期和切換頻率維持固定，減少升壓電感可提昇功率因數。因大部份功率僅經一次處理，故轉換效率提高和開關電流應力降低。在此架構中，可將返馳單元和直流-直流半級作不同電路的替換，而衍生其它不同的轉換電路。 本論文以單級並聯式升壓-反馳-反馳轉換器為對象，分析電路的運轉模式和各元件的平均切換週期信號，提出功率分配和大型電容電壓之影響參數、設計方程式和設計程序。藉著遵循設計程序，一個80瓦泛用電壓的原型被建置。實驗結果顯示，在使用範圍的最壞條件下，測得的諧波電流仍符合IEC61000-3-2 class D限制，最高大型電容電壓為415.4伏特，最大轉換效率達85.8%。 從上述電路分析得知，轉換器在半個線週期也會有兩個操作模式，其中之一模式，工作週期需隨著線電壓相位改變而改變以維持輸出恆定。這種工作週期可變之轉換器的小信號轉移函數無法以傳統頻率響應量測證實。因此，藉著建立各模式的小信號模型和提出模式分界點補償器的設計方法，使轉換器的動態響應在操作範圍內具有較小的穩態誤差、快速上升時間和大量阻尼。最後，並聯式轉換器的動態模型和所設計的補償器，以模擬和實驗在時域內得以證實。

It is known that part of the power is repeatedly processed or recycled in the conventional single-stage (S2) and two-stage AC/DC converters. Therefore, a novel S2 scheme is presented based on the parallel power factor correction (PPFC). In the scheme, the boost-flyback semi-stage containing boost cell and flyback cell is used to generate two energy processing path. The main input power flow stream is processed only by flyback cell and output to load directly. And the remaining input power stream is stored in bulk capacitor by boost cell and then transferred by DC/DC semi-stage to output for regulating output power. Theoretical analysis shows that as the boost cell and flyback cell operate in DCM and duty ratio and switching frequency are kept constant, using smaller boost inductor can result in higher power factor. Since most power is processed only once, the power conversion efficiency is improved and the current stress of control switch is reduced. The scheme can also be applied to other conversion circuits by replacing flyback cell and DC/DC semi-stage with other topology. Taking the parallel boost-flyback-flyback converter as an example, the operation modes and average switching period signals are analyzed, the key parameters of power distribution and bulk capacitor voltage, design equations, and design procedure are also presented. By follow-ing the procedure, an 80 W universal prototype has been built and tested. The experimental results show that at the worst condition of operation range the measured line harmonic current complies with the IEC61000-3-2 class D limits, the maximum bulk capacitor voltage is about 415.4 V, and the maximum efficiency is about 85.8%. It can be seen from the converter analysis, there are two operation modes in half line cycle and the duty ratio varied with line phase to keep output constant in one mode. The small sig-nal transfer function of the converter with variable duty ratio cannot be validated with con-ventional frequency response measurement. Hence, the small-signal models of operation modes are built and the compensator design at the boundary of modes is presented, the dy-namic response has small steady state error, fast rise time, and heavily damping within opera-tion range. Finally, the dynamic model and designed compensator of parallel converter are verified in time domain by simulation and experiment.