鎳矽化物應用在奈米金氧半導體元件技術之研究

Abstract

在先進互補式金氧半導體元件裡，當接觸尺寸縮小至奈米等級，源極及汲極的接觸電阻也會隨之增加。因此，金屬矽化物的技術應用在源極及汲極已經被開發用來同時降低接觸電阻及接面寄生電阻。在奈米金氧半場效電晶體的製造中，矽化製程是必須的，為了抑制源極及汲極的超淺接面形成所產生的短通道效應。所以，是否具有與矽基材完好介面特性的金屬矽化物，是在製造奈米尺寸的元件時重要的製程考量。除此之外，當閘極氧化層隨著元件尺寸縮小而縮小時，閘極金屬矽化的製程，是否會對閘極氧化層可靠度造成影響也是一個需要考量的因素。 在本論文中，主要研究的方向是，鎳矽化物與超淺接面製程、完全閘極金屬矽化製程整合的可靠度研究。首先，我們對鋯覆蓋在鎳上後形成的金屬矽化物的熱穩定性作一系列的研究。藉由鋯在金屬矽化過程中，抑制氧摻雜的能力，鎳矽化物的熱穩定性將能大大的改善。並且由穿隧式電子顯微鏡的觀測，這種方法能獲得一個平緩的矽化物與矽的介面。 然後，我們將蓋有鋯的鎳堆疊在二極體接面後形成鎳矽化物，研究用鋯覆蓋的方法對鎳矽化接面特性的影響，並與傳統用鈦覆蓋的方法作一個比較。由於熱穩定性上的改善，經由金屬矽化過程所造成的接面漏電增加，果然如預期的被抑制。並由於矽化物深度良好控制的優點，鎳矽化物形成在30奈米深的超淺接面上也如預期般的被實現了。 再者，我們對利用PH3電漿摻雜方式所形成的超淺接面，作一個探討。雖然表面雜質濃度低的缺點，能藉由一個覆蓋層來改善，但同時也造成了接面深度的增加。在我們的實驗中，我們發現，在PH3電漿摻雜後，透過短時間的退火的方式，能形成一個較少缺陷的超淺接面。 最後，我們去觀察在鎳矽化物形成在不同閘極結構上的特性。經於磷的摻雜， 能增加閘極氧化層的可靠度。因此，我們相信，對於應用在未來元件製作上，完全鎳矽化閘極仍具有潛力。

In advanced CMOS devices, as contact dimensions scale down to nanometer range, contact resistance of source and drain is increased correspondingly. As a result, the technique of metal silicides for poly gate and source/drain has been developed to reduce the contact resistance and the parasitic junction resistance as well. In nanometer MOSFET fabrication, this silicidation process requires considering to suppress short channel effect (SCE) when forming the ultra shallow source and drain junction. Therefore, metal silicides owning a perfect interfacial property with Si above an ultra-shallow junction is considered as a critical module toward the realization of nano-scale CMOS. Besides, as the oxide thickness scaling down with the device dimensions, the gate oxide reliability will also be a concern for the silicided gate process. The objective of this dissertation is to investigate the feasibility of nickel silicide integration into the formation process of the ultra shallow junction and full silicide gate. First of all, we have investigated the thermal stability of nickel silicide with Zr capping. To employ its good capability for the suppression of oxygen incorporation during silicidation process, a siginificantly improvement on the thermal stability of nickel silicide can be obtained. And a smooth interface between silicide and silicon also can be demonstrated by TEM images. Then, we combined the Zr capped on nickel silicide with the p+/n junction, and investigated the influence on junction charateristics by this capping layer compared with a conventional Ti-capped method. Due to the advantages of improvement on thermal stability, the increase of leakage current resulted from the silicidation process can be suppressed as expected. By the advantage of well-controlled silicide depth, an 30nm ultra shallow junction with nickel silicide was also accomplished as expected. Third, the formation of ultra shallow junction by PH3 plasma doped method was investigated. Its low surface concentration can be improved by a cap layer but meanwhile it will result in the increase of junction depth. In our experimental, a defect less ultra shallow junction formation by PH3 plasma doped can be achieved by short activation time. Finally, we have observed the behavior of nickel silicide gate based on different gate structures. By phosphorus incorporation, the gate oxide reliability can be enhanced. Thus, we believed that full nickel silicide gate still possesses potential for the application on future device fabrication.