低功率類比數位轉換器之設計技術

Abstract

本論文主要是探討在奈米CMOS製程之下，如何設計一個高性能且低功耗的類比數位轉換器(Analog-to-Digital Converter, ADC)來滿足系統單晶片的需求。一般而言，類比數位轉換器是由比較器、放大器、類比開關、電容、電阻和數位電路所構成。比較器與放大器是兩種較耗電的類比電路。而先進奈米製程的電晶體是愈來愈小，速度愈來愈快，功耗愈來愈低，對數位電路有極大的好處。對於低解析度(介於四位元到八位元之間)、以比較器為主的類比數位轉換器而言，可以操作在更高的取樣頻率。它們可以因製程微縮而獲益，其整體功耗主要由比較器來決定。對於中高解析度(介於十位元到十五位元之間)、以放大器為主的類比數位轉換器架構而言，由於供應電壓變低，電晶體的內部電壓增益變小，奈米製程並沒有特別的好處。相反的，類比數位轉換器所需的精準放大器電路會因低供應電壓與低內部電壓增益而消耗更多功率。因此，如何在奈米製程之下，不因為上述兩種類比電路而增加功率消耗，從而可以設計出高性能且低功耗的類比數位轉換器，則是本論文的研究重點。

在比較器的設計上，傳統的比較器電路多是使用前置放大器來降低其輸入偏移電壓。然而前置放大器的靜態功率消耗，將會大幅增加以比較器為主的類比數位轉換器的功率消耗。本論文提出一個以閂鎖器(Latch)為主的比較器電路，如此可以去除前置放大器所需的靜態功率消耗。關於閂鎖器的輸入偏移電壓問題，則藉由一個極低功耗的偏移校正迴路來改善。這種新型的比較器可被廣泛使用在比較器為主的類比數位轉換器，以大幅降低其整體功率消耗。

在放大器的設計方面，為了取代高精確放大器，本論文提出只利用簡單的開迴路低功率差動放大器來放大訊號。這種簡單的放大器可以適應CMOS製程的進展，同時也簡化類比電路的設計複雜度。然而這種放大器有增益誤差及非線性的非理想行為。在不影響類比數位轉換器正常工作下，本論文提出了一個新型的數位背景校正技術來修正上述放大器的非理想性。面對持續的製程微縮，大多數以放大器為主的類比數位轉換器都可利用本論文所提出的數位背景校正技術來縮短設計時間與降低整體功率消耗。

我們提出一個二階式類比數位轉換器之設計原型來驗證本論文所提出的技術，以達成低供應電壓與低功率消耗的要求。這個設計是一個十位元每秒一億次取樣之二階式類比數位轉換器，包含一個剩餘放大器與九十八個比較器。這個類比數位轉換器晶片是以90奈米CMOS製程製作，供應電壓是1.0伏特。在輸入信號之頻率為一百萬赫茲時，可達到75dB的無雜散信號動態範圍(SFDR)及58dB的信號對雜訊與失真比(SNDR)。利用簡單的放大器電路與前述的新式比較器電路，這個轉換器本身的整體功率消耗為6毫瓦，內部晶片面積為0.36平方毫米。而我們所提出的數位校正處理器，其功率消耗小於1毫瓦。

This thesis describes how to design a high performance and low power analog-to-digital converter (ADC) to meet the SOC requirement on nanoscaled CMOS technologies. In general, an ADC is constructed by comparators, amplifiers, analog switches, capacitors, resistors and digital circuits. Comaprators and amplifiers are two power consuming analog circuits. Digital circuits benefit CMOS scaling since transistor is smaller, speed is faster and power consumption is lower. For low resolution (between 4 and 8 bits) comparator-based ADCs, they can operate at higher sampling frequency. They also benefit CMOS scaling, and their power consumption is dominant by comparators. For medium and high resolution (between 10 and 15 bits) amplifier-based ADCs, they do not benefit from nanoscaled CMOS technologies. On the contrary, larger power consumption is necessary for accurate amplifiers in ADCs due to lower supply voltage and lower transistors intrinsic gain. Therefore, how to design high performance and low power ADCs without larger power dissipation due to comparators and amplifiers is the research emphasis in this thesis.

For comparator design, traditional design concepts usually use pre-amplifier to reduce its overall input offset voltage. However, the static power consumption of the pre-amplifier will greatly increase the comparator-based ADC power dissipation. In this thesis, we use a latch-type comparator to eliminate the static power consumption of the pre-amplifier. About the input offset voltage of a latch, we proposed a very low power offset calibration loop to improve. The proposed comparator can be widely applied to comparator-based ADCs to reduce their overall power dissipation.

For amplifier design, instead of high accurate amplifier, we proposed a simple low power open-loop differential amplifier to amplify the residue signal. This amplifier can adapt for scaled CMOS technologies and also simplify the design complexity for analog circuits. But this simple amplifier has certain non-idealities: gain error and nonlinearity. Without interrupting ADC normal operation, we proposed a new digital background calibration technique to correct these non-idealities. Most amplifier-based ADCs can use the proposed calibration technique to shorten the design time and reduce overall power dissipation for continuous CMOS scaling.

A two-step ADC prototype is manufactured to verify the proposed techniques in this thesis to achieve the requirements of low supply voltage and low power consumption. It is a 10-bit 100-MS/s two-step ADC including one residue amplifier and ninety-eight comparators. This ADC is fabricated using a 90~nm CMOS technology with 1.0 V supply voltage. At 1~MHz input frequency, this ADC can achieve the performance of 75dB SFDR and 58dB SNDR. Using a simple open-loop amplifier and proposed comparator circuits, this ADC dissipates a total power of 6~mW and occupies die area of 0.36 mm2. The power consumption of the proposed digital calibration processor is less than 1mW.