标题: 超薄层矽及锗通道元件、逻辑电路及静态随机存取记忆体之研究与分析
Investigation and Analysis of Ultra-Thin-Body Si and Ge-channel Devices, Logic Circuits and SRAM Cells
作者: 胡璧合
Hu, Pi-Ho
苏彬
Su, Pin
电子研究所
关键字: 超薄层矽通道元件;超薄层锗通道元件;鳍状电晶体;变异度;逻辑电路;静态随机存取记忆体;Ultra-Thin-Body;Silicon-On-Insulator (SOI);Germanium-On-Insulator (GeOI);FinFET;Variability;Logic Circuits;SRAM Cells
公开日期: 2011
摘要: 超薄层矽及锗通道元件(如Ultra-Thin-Body Silicon-On-Insulator (SOI), Germanium-On-Insulator (GeOI), and FinFET元件),由于其对短通道效应有较佳的控制能力及较小的变异度,使其成为未来CMOS技术可实行的元件。然而,除了这些前瞻元件在元件特性上的研究外,鲜少有此先进元件在电路上的影响之研究,本篇论文主要在分析探讨极微缩超薄层矽和锗通道元件,及其对于逻辑电路(Logic circuits)和静态随机存取记忆体(SRAM cells)的影响及分析。

首先,我们提出了一个具预测性及微缩性的解析模型来分析超薄层锗通道元件的静电完整性(electrostatic integrity),我们也考虑不同的深埋绝缘层(buried insulator, 如GeOI 及GeON)对超薄层锗通道元件的静电完整性之影响。接着我们对超薄层锗通道元件在逻辑电路及静态随机存取记忆体的漏电、效能、稳定度及变异度之影响,做了完整的研究,并与其相对应的超薄层矽通道元件电路做比较。研究发现超薄层锗通道元件能利用堆叠元件(stacking transistors)来降低其漏电(band-to-band tunneling),然而Bulk锗通道元件则无法利用堆叠元件来降低其漏电。在Vdd = 1伏特及400K时,相较于超薄层矽通道元件电路,超薄层锗通道元件在静态逻辑电路、动态逻辑电路、闩锁(latch)及多路复用器(multiplexer)都有较小的延迟(delay)。在相同的Ion设计下,相较于超薄层矽通道静态随机存取记忆体,超薄层锗通道静态随机存取记忆体之稳定度及漏电都有较小的变异性。

本论文也对超薄层矽通道元件在次临界静态随机存取记忆体(subthreshold SRAM)之稳定度及变异度做完整的研究。首先我们提出一个解析模型,能有效率的计算超薄层矽通道静态随机存取记忆体在次临界操作下的稳定度。研究显示背闸极偏压(back-gating technique)能较有效的提升次临界操作下的静态随机存取记忆体之稳定度。我们也研究了临界偏压(threshold voltage)对于超薄层矽通道静态随机存取记忆体之稳定度及变异度的影响,研究显示利用具有较小的临界偏压之元件,能同时提升稳定度及降低变异度,并提供较高的效能。超薄层矽通道元件能比传统Bulk矽元件在次临界静态随机存取记忆体提供较小的变异度并对温度有较小的敏感度。我们也发现,超薄层矽通道静态随机存取记忆体之变异度主要是受Line-Edge Roughness所影响。

除了本质变异度,我们也发现负/正偏压温度不稳定(NBTI/PBTI)所引起的时效性变异会改变最佳化鳍状电晶体(FinFET)静态随机存取记忆体的选择。我们研究超薄层鳍状电晶体利用旋转电晶体的方式来达到降低其本质及时效性的变异度,并考虑了不同的闸极介电层之影响。利用闸极到源极及汲极重叠长度的不对称性,达到增加读取稳定度而不会降低其写入的稳定度,并研究其对效能及变异度的影响。
Ultra-Thin-Body (UTB) Si and Ge-channel MOSFETs (such as UTB Silicon-On-Insulator (SOI), Germanium-On-Insulator (GeOI), and FinFET devices) are viable options for future CMOS technology owing to the superior short-channel control and inherent low device variability due to undoped channel. However, in spite of the extensive research on the device characteristics of these emerging devices, there has not been much analysis from the circuit-level perspective. The goal of this dissertation is to investigate and analyze how these emerging device structures (such as UTB GeOI, UTB SOI and FinFET devices, etc.) impact the leakage, performance, stability and variability of logic circuits and SRAM cells, and provide insights for UTB GeOI, SOI and FinFET devices/circuits design.

First, we assess the electrostatic integrity for nano-scale UTB Ge-channel MOSFETs with various buried insulator permittivity (such as GeOI and Germanium-On-Nothing (GeON)) by using a derived analytical solution of Poisson’s equations that may provide scalable and predictive results for our analysis of UTB GeOI and GeON MOSFETs devices. Based on the investigation of electrostatic integrity for UTB GeOI MOSFETs, we analyze the leakage-delay, stability and variability of UTB GeOI logic circuits and 6T SRAM cells with respect to the SOI counterparts comprehensively. The UTB GeOI circuits show better power-performance than the Bulk Ge-channel circuits, and preserve the leakage reduction property of stacking devices, while the band-to-band tunneling leakage of Bulk Ge-channel devices cannot be reduced by stacking transistors. At Vdd = 1V and 400K, the delays of inverter, dynamic gates, latch and multiplexer for GeOI circuits are smaller than the SOI counterparts. For equal Ion design, the GeOI SRAM cells exhibit better 𝝁RSNM/σRSNM and smaller cell leakage variation at both Vdd = 1V and 0.5V compared with the SOI SRAM cells.

We have also conducted research on the UTB SOI SRAM cells operating in the subthreshold region including the investigation of stability, performance, leakage and variability for 6T/8T UTB SOI subthreshold SRAM cells. An analytical framework to calculate the Static Noise Margin (SNM) for UTB SOI subthreshold SRAM cells is presented to efficiently investigate the Read/Write stability (RSNM/WSNM). The results indicate that for both the RSNM and WSNM improvement, the back-gating technique is more effective in the subthreshold mode than in the superthreshold mode. The impact of threshold voltage design on the UTB SOI SRAM cells operating near the subthreshold region is also investigated. The lower threshold voltage devices operating slightly into superthreshold region improve the stability/variability significantly and offer higher performance for ultra-low voltage SRAM applications. The intrinsic advantages of UTB SOI technology versus Bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are also demonstrated. The RSNM of UTB SOI subthreshold SRAM cells show smaller variability and less temperature sensitivity compared with that of Bulk subthreshold SRAMs. Due to the very small subthreshold swing fluctuations, Work Function Variation (WFV) shows less impact on the variability of UTB SOI subthreshold SRAMs, and the variability of UTB SOI subthreshold SRAMs is dominated by Line-Edge Roughness (LER). Our results indicate that the 6T UTB SOI subthreshold SRAM cells with back-gating technique and threshold voltage design may adequately meet/support the stability, leakage/density, and frequency requirements for intended application space of subthreshold SRAMs.

In addition to the intrinsic process variation, we demonstrate that the negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations change the optimal choice of FinFET SRAM cell surface orientations in term of the μ/σ ratio in RSNM. The combined effects of time-zero intrinsic process variability and long-term temporal variability (due to NBTI/PBTI) are considered for optimizing the FinFET device orientation combinations to improve the stability/variability of 6T FinFET SRAM cells with oxide and high-K gate dielectrics, respectively. We also investigate the 6T FinFET SRAM cells using asymmetric gate-to-source/drain underlap device to improve RSNM without degrading WSNM, and the resulting impacts on performance and variability. The conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079311532
http://hdl.handle.net/11536/40479
显示于类别:Thesis