超大型積體電路的熱分析技術

Abstract

持續縮小元件大小的互補式金氧半導體製程技術造成了在晶片上的高功率密度。這個事實導致在超大型積體電路上有很高的晶片溫度。晶片溫度將會影響到電路效能以及可靠度。此外，亦會增加電路的消耗功率。因此，許多研究者已致力於發展將溫度視為導向之一的電路最佳化以及效能分析技術。由於將熱傳視為導向的最佳化引擎需要在最佳化過程中執行許多次的熱傳分析，因此在以熱傳為導向之一的設計流程中需要一個準確且快速的熱分析器。為了提供前端設計流程的熱傳分析，此博士論文中發展了三個準確且快速的熱傳分析器。 給定了晶片上的功率分布之後，第一個分析器首先利用一組基底來表示晶片上的溫度。得到晶片溫度的表示式之後，我們發展了一個基於快速傅立葉轉換的演算法來計算出晶片的溫度分佈。基於以上的分析架構，第一個分析器也提供了堆疊晶片(stacked package)以及無接觸連線(contactless interconnection)架構的三維度積體電路之熱傳分析功能。 為了考慮製程變異以及溫度對於漏電功率的影響，第二個分析器提供了兩種熱電分析架構以快速且準確地估計晶片溫度的擾動。此外，為了提供更有意義的熱傳丈量尺度給前端設計之最佳化引擎，第二個分析器也準確且快速地提供了晶片上熱傳可靠度分布圖(thermal yield profile)。在此，熱傳可靠度分布圖為晶片溫度小於一個使用者給定之臨界溫度的機率分布圖。為了提供以矽穿孔(through silicon via)技術為架構的三維度積體電路之熱傳分析，第三 個分析器提供了一個基於查表法的分析架構。利用此查表法的分析架構，耗時的熱傳電導矩陣處理過程將可以被避免。 我們的實驗已驗證了以上三個熱傳分析器具有高度的估計準確率以及分析效能。

The continuously scaling down of the CMOS technology results in high on-chip power density, and this fact leads to high on-chip temperature in modern very large scale Integration (VLSI) circuits. On-chip temperature influences the performance and the reliability, and it also increases the power consumption of the circuits. Therefore, researchers have devoted to thermal-aware optimization techniques. Since the thermal-aware optimization engines require performing numerous thermal simulations in their optimization loops, an efficient and accurate thermal analyzer is essential for thermal-aware design flow. In this dissertation, three accurate and efficient thermal simulators for early stage thermal-aware design engines are proposed. Given the deterministic on-chip power profile, the first simulator represents the on-chip temperature profile by a set of bases. Then, a fast Fourier transform based algorithm is developed to obtain the on-chip temperature profile. Based on the above simulation framework, the first proposed simulator also provides the thermal simulation for the stacked-chip or the contactless interconnection based three-dimensional integrated circuits (3-D ICs). To take into account the impacts of the process variation and the temperature to leakage powers, the second simulator provides two electro-thermal simulation frameworks to accurately and efficiently predict the fluctuation of on-chip temperature profile. Moreover, to ensure the on-chip thermal reliability and provide more meaningful thermal costs for thermal-aware design engines, the second simulator can efficiently deliver the thermal yield profile, which is the probability profile of the temperature being less or equal to a user specified threshold temperature. To provide the thermal estimation for early stage thermal-aware design engines for the through silicon via based 3-D ICs, the third proposed simulator provides a look-up table based thermal simulation framework. With the look-up table based framework, the time consumed dealing processes for the thermal conductance matrix of the equivalent thermal circuit can be avoided. The experimental results have demonstrated the high-accuracy and high-efficiency of all the three proposed thermal simulators.