金氧半及鰭式場效電晶體閘極穿隧電流之先進模擬及其潛在應用

Abstract

應用於傳統多晶矽閘極以及現代高介電金屬閘極場效電晶體的直接穿隧電流和Fowler-Nordheim 穿隧電流的解析模型，已在本文建構完成。除此之外，有關缺陷如何提供額外穿隧電流的相關模型也同時被探討及建立。藉由自力完成的量子模擬器所計算出的能階值及已知的等效質量，此穿隧電流模型的可靠度已被完整的驗證。尤其，基於此模型，先進技術的潛在應用則首次被提出。藉由此嶄新提出的技巧，製程及材料參數可以被正確的萃取，而此得到的參數則可以對元件的組成本質及其對製造流程的相關性質有進一步的了解。 首先，對於一閘極氧化層為1.27奈米厚之p型金氧半場效電晶體，其淺溝槽隔離的製程會對通道內部造成壓縮應力，我們發現，實驗的電洞穿隧電流會隨著此壓縮應力增加而增加。然而，在文獻中，藉由外加應力所導致價電帶的能帶分裂的物理圖像，可以合理的解釋：電洞穿隧電流隨著外加壓縮應力增加而減少，但這和我們的實驗結果卻是相互牴觸。為了解釋這不一致的趨勢，我們把量子模擬器和穿隧電流模型加以整合，並驗證此模擬器之正確性。對於此相反趨勢，藉由模擬結果和實驗結果相互的比較探討，導引出一個物理解釋：淺溝槽隔離不但會造成通道內部的壓縮應力，並同時阻礙氧化的成長，而氧化層厚度隨著應力的改變量，精確至0.001奈米，被我們的穿隧電流模型偵測得到。氧化層隨著淺溝槽隔離壓縮應力而變薄，大量增加了穿隧電流，因此反轉了文獻中，電洞穿隧電流隨著外加壓縮應力增加而降低的趨勢。 接下來，我們在一個樣本為TaC/HfSiON/SiON高介電金屬閘極之n型金氧半場效電晶體量測的閘極漏電流中，發現漏電流中，有一個過渡區域。而其對應的dlnIg/dVg-Vg圖形可以顯著的呈現此過渡區域。在此，我們有系統的模擬此區域的穿隧電流及其dlnIg/dVg-Vg的特性，我們發現可以因此正確的萃取出一些重要的材料參數，如金屬的功函數，高介電閘極層的電子親和力，還有電子的穿隧等效質量。首先，我們完成了直接和F-N穿隧電流的計算，並提出了一個如何模擬和重現實驗值的指導方針。藉由此漏電流模擬的指導方針，相對應的材料參數被正確的萃取出來，甚至在更高的溫度下還有電場下我們的模擬結果仍維持其正確性。我們也提出一個結論，若在做漏電流模擬時，沒有針對其dlnIg/dVg-Vg的特性做模擬和匹配，有可能會因此萃取出錯誤的材料參數。因此，dlnIg/dVg-Vg的特性模擬，對於高介電金屬閘極金氧半場效電晶體的穿隧電流模擬是非常重要的。除此之外，我們發覺，藉由表面缺陷提供的穿隧電流，對於要完整重現實驗漏電流，是必須加入探討的。 此外，其等效氧化層厚度為0.75奈米的TiN/HfO2/SiON高介電金屬閘極之n型金氧半場效電晶體的閘極漏電流及其dlnIg/dVg模擬和匹配在本文中被完整呈現。首先，我們發現無論是HfO2還是HfSiON的等效穿隧質量都為0.03 m0。0.03 m0是目前文獻中最低的等效質量值，而此值和高介電閘極層的材料無關，這些結果指出了一些目前無法解釋的物理現象。在模型中，藉由將一層其介電值、等效穿隧質量、電子穿隧能障都逐步變化的過渡層導入HfO2高介電層和SiON介面層之間，實驗值可以完美的被模擬器重現。藉由模擬值和實驗比較的結果，然而我們發現，HfSiON/SiON之間則沒有此過渡層。最後，電子藉由IL/Si介面的缺陷而產生的穿隧電流，對於整體穿隧電流的重要性在本文中則被突顯出來。 再一次，對於等效氧化層厚度為1.5奈米的TaC/HfSiON/SiON還有等效氧化層厚度為0.85奈米的TiN/HfO2/SiON高介電金屬閘極之p型金氧半場效電晶體其量測出的閘極、汲極/源極、基極電流，我們對其做廣泛完整的模擬及重現。整合分別來至於通道反轉層載子和IL/Si介面缺陷中載子的穿隧電流，再加上藉由在介面層中的缺陷(可以達到最大穿隧機率)，而造成的缺陷輔助穿隧電流，TiN/HfO2/SiON p型金氧半場效電晶體的漏電流可以被完美的重現。然而，缺陷輔助穿隧電流，沒有在TaC/HfSiON/SiON p型金氧半場效電晶體的量測電流中被發現。除此之外，在本文中也完成了，模擬電子從金屬端穿隧到基極端所造成的穿隧電流。最後，額外的dlnIg/dVg-Vg圖型模擬，其對於正確萃取材料參數的重要性也在本文中被突顯。 最後，一個適用於等效氧化層厚度為0.8奈米的高介電金屬閘極鰭式場效電晶體的先進模型被驗證。首先，適用於雙閘極電晶體結構的解析模型被建立。接下來，我們整合並完成Ig-Vg、Cg-Vg、和dlnIg/dVg-Vg實驗圖型的模擬和重現，得到了數個值得住意的結果。首先，只有在模擬器中，高介電層和介面層之間導入了一層過渡層，實驗值才可以被精確的模擬，而穿隧式電子顯微鏡所拍攝的圖片可以支持此論點。第二點，我們萃取出的高介電材質的等效穿隧質量為0.02 m0。第三點，鰭式電晶體包含了(001)和(110)的晶面，就算如此，我們藉由重現其穿隧電流所萃取得到的材料參數，和相同製程下在平面式n型金氧半場效電晶體所萃取得到的參數是一致的。最後，藉由模擬從表面缺陷穿隧至金屬閘極之穿隧電流，低電壓下的實驗漏電流可以被完美的解釋。

Analytic gate direct tunneling and Fowler-Nordheim tunneling current model for conventional polysilicon gate oxide MOSFETs and present-day metal-gate/high-k/IL gate stack CMOSFETs and n-FinFETs is established. In addition, trap related tunneling is incorporated as well. Validity of the model, with the known effective masses and subband energies created using an in-house quantum confinement simulator, is thoroughly corroborated. Particularly, advanced techniques on the application of the model are proposed for the first time. Resulting process and material parameters of the device under study not only can provide new insight into underlying manufacturing process but also can be quantitatively more accurate than those obtained from conventional method without advanced techniques in this work. At first, on a nominally 1.27-nm thick gate oxide p-MOSFET with STI longitudinal compressive mechanical stress, experimental hole gate tunneling current exhibits an increasing trend with STI compressive stress. However, this is exactly opposed to the currently recognized trend: Hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain altered valence-band splitting. To determine the mechanisms responsible, the combination of the model and a quantum strain simulator is established and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: A reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain altered valence-band splitting. Next, for planar bulk n-MOSFET low-EOT (1.4 nm) TaC/HfSiON/SiON high-k gate stacks, there is a transition region in the electron gate tunneling current Ig, as characterized by a plot of dlnIg/dVg versus Vg. Here, we systematically construct a new fitting over the region, which can accurately determine the material parameters including the metal workfunction, the high-k electron affinity, and the tunneling effective masses of electrons. First of all, a calculation of gate current due to electron direct tunneling and/or Fowler-Nordheim tunneling from the inversion layer is performed, yielding the guidelines of the fitting. The underlying material parameters are extracted accordingly and remain valid for higher temperature and gate voltage. We also demonstrate that the conventional method without the dlnIg/dVg fitting might lead to erroneous results. Thus, dlnIg/dVg fitting is crucial to the metal-gate high-k material parameters assessment. In addition to electron tunneling from inversion layer to metal electrode, additional tunneling component via the interface states is shown to be significant in reproducing experimental gate leakage current. Further, for 0.75-nm EOT TiN/HfO2/SiON nMOSFETs, experimental gate tunneling current and its dlIg/dVg fittings are presented. First of all, electron tunneling effective mass in HfO2 dielectric lies at around 0.03 mo, which is consistent with the HfSiON counterpart. This dictates some unexplained physical mechanisms, which not only are common to both HfO2 and HfSiON but also are responsible for unconventionally low effective mass in tunneling. Furthermore, a graded transition (intermixing) region from SiON interfacial layer to HfO2 high-□ can ensure a good fitting. This suggests that a transition layer exists in HfO2 based high-k gate stacks whereas it does not exist in HfSiON/SiON gate stacks. The importance of electron tunneling via IL/Si interface states in overall gate leakage is highlighted. For both 1.5 nm-EOT TaC/HfSiON/SiON and 0.85nm-EOT TiN/HfO2/SiON gate dielectric p-MOSFET counterparts, a comprehensive fitting of measured tunneling current components through source/drain, bulk, and gate is performed. Combining electron direct and F-N tunneling from both the inversion layer and IL/Si interface states with the trap-assisted tunneling (TAT) current around the favorable trap (in interfacial layer for the maximum tunneling probability there), the experimental hole tunneling current for TiN/HfO2/SiON gate dielectric pMOSFETs is reproduced well. However, TAT mechanism does not exist in the experimental gate current data for TaC/HfSiON/SiON gate stacks pMOSFETs. The fittings of the substrate current stemming from gate-to-substrate electron tunneling for both test devices are also conducted. Furthermore, the importance of extra dlnIg/dVg-Vg fitting to ensure accurate assessment of gate material parameters is highlighted as well. At this point, we will demonstrate advanced modeling in 0.8-nm EOT HfO2 based high-k/metal-gate n-FinFETs. First of all, an analytic model suitable for double-gate structure is newly constructed. Then, the combination of Ig-Vg, Cg-Vg, and additional dlnIg/dVg-Vg curve fittings leads to several remarkable results. First, only with a transition layer between high-k and interfacial layer can a good fitting be obtained, as supported by TEM analysis. Second, the tunneling effective mass in HfO2 based high-k dielectric is around 0.02 m0, a minimum value reported to date. Third, all extracted gate material parameters remain valid, taking into account the difference between (001) and (110) surfaces, for the planar bulk n-MOSFET counterparts formed on the same wafer. Finally, the experimental electron tunneling current at low gate bias can be fitted well by adding the role of tunneling from IL/Si interface states to metal gate.