碳摻雜製程與高性能多晶矽奈米線薄膜電晶體之研究

Abstract

在本論文中，吾人首先研究碳摻雜製程對於矽化鎳薄膜之熱穩定性、矽化鎳接觸之n+/p接面之影響，並利用低溫碳離子佈植技術搭配固態磊晶退火方式，完成碳化矽薄膜的製作。其次，吾人成功製作出閘極長度僅三十奈米之高性能多晶矽奈米線薄膜電晶體，藉由元件結構設計，能得到良好的短通道特性與極高的導通電流值。吾人也探討元件尺寸大小對於多晶矽薄膜電晶體之電流傳導機制的影響，並用來解釋所觀察到的兩種自我加熱（self-heating）現象。最後在小尺寸多晶矽奈米線薄膜電晶體上，吾人首次觀察到隨機電報雜訊（random telegraph noise）現象，並藉由模型推導與高溫測量，證實晶界陷阱也能造成隨機電報雜訊現象。 我們採用電漿浸潤式離子佈植法（plasma immersion ion implantation），將碳離子植入至矽基材表面，此技術具備高劑量摻雜與低能量植入的優點，但在低能量與長時間的佈植過程中，同時會沈積類鑽碳膜（diamond-like carbon）在矽基材表面上，阻擋矽化鎳的形成，因此，必須將反應溫度提升至800 °C，才能形成矽化鎳。另一種離子植入方式為傳統離子佈植法，碳離子植入矽基材表面能改善矽化鎳薄膜之熱穩定性，特別是高溫下的結塊現象，其改善效率與存在於矽化鎳與矽介面間的碳原子數量相關，在足夠的碳原子濃度下，矽化鎳薄膜的結塊溫度與晶相轉換溫度高達850 °C以上。即使矽化鎳薄膜厚度減薄時，碳摻雜技術仍能有效提升矽化鎳薄膜之結塊溫度高達300 °C。然而，對於矽化鎳接觸之n+/p接面來說，矽基材表面經過高劑量（5x1015 cm-2）的碳離子佈植與高溫退火後，仍有許多殘餘缺陷存在於矽基材表面，在矽化鎳反應的過程中，大量的鎳原子能經由這些缺陷快速擴散並抵達接面空乏區，造成n+/p接面漏電流增加。 其次，藉由最佳化碳離子佈植與低溫固態磊晶退火製程，我們已經成功製作出取代位置上的碳原子濃度百分比為1.046 %的碳化矽薄膜。然而，過高的碳原子濃度會減緩非晶矽區域的固態磊晶再結晶速率，造成不完全的再結晶與磷摻雜物重新分佈的現象，此兩因素皆會造成再結晶的碳化矽薄膜的片電阻值上升。 整合全包覆式閘極（gate-all-around）、超薄多晶矽奈米線基體與修正型蕭基能障（modified Schottky barrier）源汲極結構後，成功實現了閘極長度僅三十奈米的高性能多晶矽奈米線薄膜電晶體，具備良好的轉移曲線特性。碳離子佈植技術能解決極薄的全矽化鎳源汲極區域發生的結塊現象。我們也探討短通道效應、窄線寬效應及氨氣電漿處理對於元件直流特性之影響。當進一步採用高介電常數二氧化鉿來取代傳統二氧化矽閘極氧化層時，高性能多晶矽奈米線薄膜電晶體在低閘極電壓（2.587 V）與汲極電壓（1 V）操作下，其驅動電流值高達549 μA/μm，為已發表過的文獻中最高的驅動電流值。這些實驗結果開啟多晶矽薄膜電晶體應用於三維積體電路（three-dimensional integrated circuits）的可能性。 我們也發現多晶矽薄膜電晶體中存在不同的電流傳導機制，大尺寸多晶矽薄膜電晶體的電流傳導機制為熱游離發射，然而，由於晶界效應消失，小尺寸多晶矽薄膜電晶體的電流傳導機制會轉變成飄移擴散模型。因此，當多晶矽薄膜電晶體發生自我加熱效應時，大尺寸多晶矽薄膜電晶體的導通電流會增加，但是小尺寸多晶矽薄膜電晶體的導通電流會下降。 最後，我們分析小尺寸多晶矽奈米線薄膜電晶體的隨機電報雜訊，包含時域分析與頻域分析。除了氧化層陷阱與介面能態外，我們也推導由晶界陷阱所導致之載子數目擾動模型，並藉由高溫測量證實晶界陷阱也能造成隨機電報雜訊現象，未來欲將多晶矽薄膜電晶體實際應用到三維積體電路或是非揮發性記憶體時，此晶界陷阱導致之隨機電報雜訊必須納入考慮。

In this dissertation, we studied the impact of the carbon (C) doping technology on the thermal stability of nickel monosilicide (NiSi) and the Ni-silicide-contacted n+/p junction. Moreover, using the low-temperature C ion implantation (I/I) technique followed by solid phase epitaxy (SPE) annealing, silicon-carbon (SiC) layer with high concentration of substitutional carbon could be achieved. Then, we successfully fabricated the high-performance poly-Si nanowire (NW) thin-film transistor (TFT) with a physical gate length (LG) of 30 nm. Good short-channel characteristics and high driving capability could be obtained by structural engineering. Furthermore, we discussed the influence of device geometry on the current transport mechanism. Two self-heating phenomena observed in poly-Si TFTs could be explained by different current transport mechanisms. Finally, we first observed the random telegraph noise (RTN) phenomenon in small-area poly-Si NW TFTs. The RTN phenomenon could also arise from the capture and emission of a carrier by the grain-boundary trap, which was confirmed by model derivation and high-temperature measurements. We adopted the plasma immersion ion implantation (PIII) technology to implant C ions into the Si substrate surface. PIII has the advantages of high ion fluences and low energy implantation. However, for low energy and long period PIII process, a diamond-like carbon (DLC) film simultaneously deposited on the Si substrate surface and prevented Ni-silicide formation. Therefore, the silicide formation temperature must be raised to 800 °C. Another I/I method used in this study is the conventional C I/I process. Implanting C ions into the Si substrate surface could improve the thermal stability of the NiSi film, especially for the agglomeration phenomenon at high temperatures. The efficiency of improvement is related to the amount of C atoms at the NiSi/Si interface. With sufficient C concentration, the agglomeration and phase transformation temperatures of the NiSi film could be raised to higher than 850 □C. Even if the Ni-silicide film was thin, the C doping technology could still effectively raise the agglomeration temperature of the Ni-silicide film at high as 300 □C. Moreover, For the Ni-silicide-contacted n+/p junction, after high-dose (5x1015 cm-2) C I/I and high-temperature annealing, there were still many residue defects existing in the Si substrate surface. During the formation of Ni silicide, a large number of Ni atoms would rapidly diffuse and arrive at the junction depletion region via these defects, which caused the increase of the n+/p junction leakage current. We have successfully fabricated the SiC film with substitutional C concentration of 1.046 % by optimizing the C I/I and SPE annealing processes. Nevertheless, excess C concentration retarded the SPE regrowth rate in the amorphous Si region. Therefore, the incomplete recrystallization and phosphorus (P) dopant redistribution phenomena were observed and both resulted in the increase in sheet resistance of the recrystallized SiC film. After the integration of the gate-all-around (GAA) structure, ultra-thin and narrow poly-Si body, and modified Schottky barrier (MSB) source/drain (S/D) junction, the high-performance poly-Si NW TFT with LG= 30 nm was successfully realized. It had good transfer characteristics. The fully-Ni-silicided S/D was agglomerated owing to the thinner NiSi film, which could be resolved by the C I/I technology. We also discussed the effects of the short channel, narrow width, and ammonia (NH3) plasma treatment on the dc characteristics of the poly-Si NW TFTs. When the silicon dioxide (SiO2) gate dielectric was further replaced by high permittivity (high-□) hafnium oxide (HfO2), the driving current of the high-performance poly-Si NW TFT biased at low gate and drain voltages (VGS= 2.587 V and VDS= 1 V) was up to 549 μA/μm. This value is the highest among the published literature. These experimental results open the possibility that poly-Si TFTs could be applied in three-dimensional integrated circuits (3D IC). We also found different current transport mechanisms in poly-Si TFTs. The current transport mechanism in large-area poly-Si TFTs is considered as thermionic emission. However, the current transport mechanism in small-area poly-Si TFTs transformed into the drift-diffusion model owing to the disappearance of the grain-boundary effect. Therefore, as the self-heating effect (SHE) occurs in poly-Si TFTs, the on-state current increases in large-area poly-Si TFTs but decreases in small-area poly-Si TFTs. Finally, we analyzed the RTN phenomenon in small-area poly-Si TFTs, such as time-domain and frequency-domain analysis. In addition to the gate oxide trap and the interface state, we also derived the carrier number fluctuation model induced by the grain-boundary trap. By high-temperature measurements, we proved that a capture and a release of a carrier by the grain-boundary trap could also cause the RTN phenomenon. As poly-Si TFTs are applied to future 3D IC or 3D nonvolatile memories, the RTN phenomenon induced by the grain-boundary trap should be considered.