新穎反轉式及無接面多閘極多晶矽奈米線薄膜電晶體特性與應用的探討

Abstract

本篇論文研究獨立雙閘極(independent double-gated)多晶矽奈米線薄膜電晶體操作於低汲極(drain)偏壓時，雙閘控制模式相對於單閘控制模式而言有較佳輸出電流的主要原因。實驗數據以及理論分析結果顯示，當多晶矽奈米線元件操作於雙閘模式控制之下，對於通道中晶粒邊界與缺陷所造成之位能障(grain-boundary potential barrier)具有較佳的調控能力，因而可獲得相較單閘操作下為佳的元件特性。 另一方面，本研究也探討將獨立雙閘極機制應用於SONOS記憶體元件中的可能性。由於獨立雙閘極SONOS記憶體元件具有兩個可以獨立操作的閘極，所以有兩種讀取模式可供選擇。論文中分析了兩種不同讀取模式對感測窗口大小(memory window)特性的影響。本論文製作的元件採用的雙閘極介電層分別為二氧化矽以及二氧化矽-氮化矽-二氧化矽堆疊層。當選用具二氧化矽-氮化矽-二氧化矽堆疊層為閘介電層之閘極當驅動閘極(driving gate)時，SONOS記憶體元件具有比較大的感測窗口，但是，其大小與施加於輔助閘極的偏壓無關。根據這些分析，本研究提出了幾種以無摻雜或重摻雜矽薄膜為通道且具獨立雙閘極之先進非揮發性記憶體結構，其主要特徵為具有一共用輔助閘來增進性能。 除了獨立雙閘極多晶矽奈米線薄膜電晶體外，運用全包覆式閘極(gate-all-around)無接面(junctionless)多晶矽奈米線薄膜電晶體的電流-電壓(I-V)量測，我們也發展了ㄧ個可用於檢測重磷摻雜多晶矽奈米線通道的活化摻雜濃度(active doping concentration)、遷移率(mobility)及分布於閘極介電層與通道間的表面二氧化矽閘極介電層電荷密度(interface oxide charge density)的量測方法。利用此方法獲得的重磷摻雜多晶矽奈米線通道特性分析結果與實施於平面無接面薄膜電晶體的電容-電壓(C-V)量測分析結果相當ㄧ致。相較於對重磷摻雜多晶矽塊材進行霍爾量測(Hall measurement)所獲得的分析結果，上述兩個方法皆顯示較低的活化摻雜濃度以及大量負的表面二氧化矽閘極介電層電荷密度。其主要原因推估為磷於二氧化矽閘介電層與多晶矽通道間介面的偏析(segregation)現象。 此外，考慮到無接面場效電晶體的實際應用，本研究也發展了一個理論模型，可用於描述雙閘極無接面場效電晶體的臨界電壓(threshold voltage)與次臨界電流(subthreshold current)。其計算結果顯示，此模型可以準確的描述雙閘極無接面場效電晶體導通通道長度從100 nm微縮至22 nm時，元件呈現的臨界電壓下降效應(threshold voltage roll-off effect) 。 除了探討一般的無接面場效電晶體，考量蕭特基位障(Schottky-barrier)電晶體於非揮發性記體元件的應用潛力，本研究也提出了一種新穎的非對稱蕭特基位障電晶體。此非對稱元件具備了蕭特基位障於源極(source)端，然而，其導通通道與汲極皆為重n型摻雜。計算結果顯示，其非對稱的特性使得此蕭特基位障電晶體顯示出單極(unipolar)的傳輸特性以及低的漏電流，但是其位於源極端的蕭特基位障也劣化了元件的輸出電流以及操作於擬次界區(pseudo-subthreshold region)的次臨界擺幅(subthreshold swing)。而此次臨界擺幅的劣化可藉由薄化導通通道以及閘極介電層來獲得改善。除此之外，本研究也提出了修正的微縮長度(scaling length) “λ”概念，來描述導通通道以及閘極介電層的厚度對位於擬次界區的次臨界擺幅所產生的影響。 最後，本論文在全包覆式閘極反轉模式 (inversion-mode)多晶矽奈米線元件常溫量測中發現獨特的低於60 mV/dec的次臨界擺幅現象。其主要原因推估與下面兩項描述相關。第一、trap-assisted band to band tunneling (BTBT) current於汲極端產生了大量的電洞，其中部分被擷取於晶粒邊界之缺陷所造成之能階狀態中。第二、後續當元件操作於次臨界區(subthreshold region)時，擷取的電洞被中和。然而，我們的量測數據顯示，當元件通道長度逐漸微縮或者包覆式閘極遭單閘取代時，此獨特現象將逐漸消失。

In this dissertation, we study the characteristics of independent double-gated (IDG) polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) with focus on the physical mechanism responsible for the superior output current under double-gated (DG) mode of operation over that under single-gated (SG) mode at a small drain voltage. The experimental data and theoretical analysis identify that the root cause is related to the more efficient modulation of grain boundary barrier height of poly-Si channels under DG mode of operation. On the other hand, the feasibility of applying such IDG scheme to silicon–oxide–nitride–oxide–silicon (SONOS) flash memory is also explored. Two different read modes can be adopted in such IDG poly-Si NW SONOS device with the two independent control gates. Special attention is paid to the analysis of memory window under different read modes. The fabricated device has oxide and oxide-nitride-oxide (ONO) stack as dielectrics for the two independent gates, respectively. Our analysis and experimental data show that a larger memory window is obtained when the gate with ONO stack as dielectrics is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the auxiliary gate. Based on this finding, several novel IDG Flash structures with undoped or heavily doped silicon channels and a common auxiliary gate are proposed. Next, based on the measured I-V characteristics of gate-all-around (GAA) poly-Si NW junctionless (J-less) TFTs, we develop a methodology capable of extracting the values of active doping concentration, mobility, and interface fixed charge density of the in situ phosphorous-doped poly-Si NW channel. The experimental results show lower value of active doping concentration as compared to that obtained from Hall measurements performed on blanket thin films. Moreover, a highly negative interface oxide fixed charge density is found as well. These measured properties of the heavily doped poly-Si NWs are compared with the results of C-V measurements performed on planar J-less transistors with an ultra-thin channel. Close agreement is obtained between these two schemes. Segregation of phosphorous at gate oxide/NW interface is postulated to be the responsible mechanism for the observed phenomena. In this dissertaton, we also develop an analytical model of threshold voltage (Vth) and subthreshold current for DG J-less transistors by solving the two-dimensional Poisson’s equation. The Vth roll-off effect of DG J-less transistors with channel length from 100 to 22 nm can be well described through the proposed model as the channel thickness is thinned to 8 nm. In addition, we also propose a new asymmetric n-channel SB transistor (ASSBT) which features SB only on the source side, while the channel and drain are both n+ doped. Our calculation results show that such a device exhibits unipolar behavior and low off-state leakage current owing to the elimination of SB originally presenting on the drain side. However, aggravated subthreshold swing (SS) in the pseudo-subthreshold region and degraded output current are found because of the SB source. Based on the calculation results, the aggravated SS can be improved by thinning the thickness of silicon channel or gate oxide. A modified form of scaling length (λ) concept is introduced to describe the impacts of structural parameters and gate configurations on the SS characteristics in the pseudo-subthreshold region. Finally, we report, for the first time, an abnormal phenomenon showing sub-60 mV/dec SS found in GAA inversion-mode (IM) poly-Si NW TFTs at room temperature. The responsible physical mechanism related to the trapping of excessive holes generated by the high trap-assisted band-to-band tunneling (BTBT) current and later recombination of these trapped holes when operating in the subthreshold regime is suggested. Moreover, the experimental data also indicate that such an unexpected phenomenon is relieved or even negligible with the decrease of channel length or the replacement of GAA configuration by a single-gated one.