應用於多頻段與超寬頻通訊之射頻接收電路設計與分析

Abstract

本篇論文提出了數種適用於多頻段與超寬頻通訊系統的0.18 微米互補式金氧半製程射頻積體電路元件之架構、分析與設計。其中包含了 (1) 兩個使用諧振切換與雜訊消除電路的多頻帶低雜訊放大器；(2) 具鏡像頻率抑制混頻器的設計；(3) 三個低功率超寬頻低雜訊放大器的分析與設計；(4) 採用降低相位雜訊技術的壓控振盪器電路。 多頻帶低雜訊放大器藉由切換的概念來實現多頻帶操作，其能有效地減少系統面積來降低製作的成本，並且於第二個多頻帶低雜訊放大器設計中，利用回授式雜訊相消電路能同時達到輸入匹配以及改善雜訊指數的效果。另外在所設計電路的主動元件中額外引入一阻值較大的基極電阻，以避免雜訊從電晶體的基極端交互流竄而惡化電路本身的雜訊指數特性。在不額外增加晶片面積、製程步驟、以及直流功率損耗的前提之下，採用此雜訊降低電阻於2.5 GHz操作頻帶時，能達到32%的雜訊指數改善效果，可廣泛地應用在現今低雜訊放大器的設計。 其次，本論文提出了一個具鏡像頻率抑制的吉伯特降頻混頻器。相對於傳統的Hartley或Weaver鏡像頻率抑制電路架構，此混頻器能大幅地降低直流功率損耗與電路設計的複雜度。並且搭配一負阻抗產生主動電路，藉由合適的負阻抗來消除濾波器的正電阻以提升其品質因數Q，進而增進鏡像訊號抑制的效果。此混頻器於2.4/5.2 GHz使用頻段的量測結果如下：轉換增益 (conversion gain) 為10.5/11 dB、一階與三階交叉點的輸入功率 (IIP3) 為4.9/-5.2 dBm、單邊雜訊指數 (SSB NF) 為10/13 dB、鏡像頻率抑制效果可達36/45 dB。 再其次，由於超寬頻系統的訊號強度遠低於IEEE 802.11 a/b/g以及1.8 GHz DCS/ GSM系統，因此首先我們在第一個超寬頻低雜訊放大器中提出具頻帶外訊號抑制能力的輸入匹配網路去壓制其他系統所造成的干擾。另外我們在第二個低雜訊放大器電路中，藉由使用一個回授結構以及雙頻帶主動式低功率帶拒濾波電路進一步地提升抑制干擾訊號的效果。經改良所設計出的低雜訊放大器在1.8/2.4/5.2 GHz能夠達到最大抑制效果為55/48/45 dB。另一方面，由於減少輸入端損耗元件的使用能有效地改善電路的雜訊指數，在此引入了電晶體的寄生電容來達到超寬頻輸入匹配特性，當輸入回返損耗 (input return loss) 大於10 dB以上時，其頻帶內最大增益為16.2 dB，最小雜訊指數為2.3 dB，且總直流功率損耗僅為6.8 mW。 最後提出的是具降低相位雜訊參數之壓控振盪器電路，藉由最佳化被動元件尺寸以及額外設計的二次諧波抑制電容與基極偏壓，整體電路性能參數FOM (figure of merit) 能達到-190 dBc/Hz。此壓控振盪器晶片所使用的面積為0.15微米平方，且由實驗的結果分析得知，總功率耗損僅為1.9 mW，而在1 MHz offset時其相位雜訊約為-119 dBc/Hz。

In this dissertation, the design methodologies and implementations of RF receiver circuits for multiband and ultra-wideband communication applications are proposed. There are four parts in this thesis, including: (1) the design of two triple-band low-noise amplifiers (LNAs) using switched resonators and a noise cancelation technique, (2) the design of dual-band image rejection mixer, (3) the analysis and design of three low-power UWB LNAs, and (4) the design of voltage-controlled oscillator (VCO) with phase-noise improvement. First of all, the design of two triple-band LNAs with switched resonators is presented and fabricated in the TSMC 0.18-μm CMOS process. The proposed triple-band LNAs are demonstrated the feasibility to effectively decrease the size of multi-band RF systems by using a switched component. In addition, a considerable noise power diminution in MOS devices with an additional larger substrate resistor is presented in the second approach of the triple-band LNA. A 32% noise reduction of MOS devices can be achieved at 2.5 GHz without extra chip area, CMOS process steps and dc power. This noise reduction technique in MOS device is very promising in the nowadays LNA designs. Secondly, this thesis presents a 2.45/5.2 GHz dual-band Gilbert downconversion mixer with image rejection function is presented, which is implemented in the 0.18-μm CMOS technology. The proposed differential dual-band image rejection circuitry is employed for the 2.45/5.2 GHz WLAN application to effectively diminish the dc power consumption and complexity of circuit design compared to the traditional Hartley or Weaver architectures. Moreover, the cross-connected pair consisted of NMOS and PMOS transistors in the proposed notch filter will further ameliorate the image rejection capability. The IC prototype attains conversion gain of 10.5/11 dB, IIP3 of -4.9/-5.2 dBm for RF= 2.45/5.2 GHz and IF=500 MHz while the image rejection ratio is better than 36/45 dB in the whole operation bandwidth. Thirdly, three low-power UWB LNAs using 0.18-μm CMOS technology are presented. Due to the FCC’s stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrow-band interferers such as the IEEE 802.11 a/b/g WLAN, and the 1.8 GHz DCS/ GSM. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band interference for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low power active inductors will further attenuate the outband interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, 15 dB power gain, and 3.5 dB minimum noise figure can be measured while consuming dc power of only 5 mW. On the other hand, to further improve the noise figure performance of the above out-band rejection LNAs, a new matching technique is presented in the third UWB LNA. The proposed broad-band input match network can be obtained easily by selecting an appropriate width of the transistor, which could effectively avoid the usage of the low-Q on-chip inductors in the input network. The IC prototype achieves good performances: 16.2 dB maximum power gain, better than 10 dB input return loss, and 2.3 dB minimum noise figure while consuming dc power of only 6.8 mW. Finally, a low-power 5.25 GHz VCO with phase-noise improvement is designed in a 0.18-μm CMOS 1P6M process. Due to the usage of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of the transistor, a good figure of merit (FOM) of -190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a power consumption of 1.9 mW and active chip area of 0.15 mm2. The measured phase noise at 1 MHz offset is about -119 dBc/Hz.