設計、製作及測試CMOS製程相容之微機電邏輯閘

Abstract

本論文提出了設計，製作和測試一種創新型的微機電邏輯閘。此元件結合了微機械開關(MEMS Switch)的優點與IC邏輯閘的布林代數(Boolean Algebra)運算功能，所以可預期此元件將比現存的微機械開關更廣泛的被使用。目前微機電邏輯閘的設計並不多，且大部分採用MOS-like的機構來完成，意即其設計需要四個以上具備MOS功能的微機械結構，才能完成一NAND閘或NOR閘的邏輯功能，本論文所提出的元件設計只需透過不同的電壓配置方式，即可利用單一的機械結構表現出NAND閘或NOR閘的邏輯功能，因此能改善製作良率及減少佈局面積(layout)浪費等問題。 為了要實現此一微機電邏輯閘，元件的製程設計必須符合其特殊的結構設計需求，包括：金屬-金屬接觸、在一平坦的懸浮機構上實現多重電性、低溫製程溫度(<400℃)、與CMOS製程整合能力。因此，本研究提出以二種不同的製程來設計、製作此一新式的微機電邏輯閘。此兩種製程分別為自行研發的製程及專業製程代工廠所提供的CMOS-MEMS製程。由於製程中薄膜的殘留應力可能使得結構產生彎曲變形，使得所設計的元件的邏輯功能失效。因此，在自行研發的製程設計中，我們提出了一個新式in situ薄膜應力校正法來幫助並校正元件製程的開發；而在CMOS-MEMS製程設計中，我們則是透過選取不同金屬及氧化層，來實現一個平坦的懸浮結構。在利用自行研發的製程中，所設計的元件尺寸為長250 μm，寬100 μm及3.97 μm的間隙。根據實驗的結果，此元件可在切換頻率為100 Hz，驅動電壓大小為25/-25V下，實現NAND即NOR邏輯功能。此外，本論文亦量測了元件許多的特性，包含了元件的切換能量耗損、元件開關在導通及不導通狀態時的電阻值、元件的壽命與元件的共振頻率。在CMOS-MEMS製程中，我們研究了不同的溼蝕刻液來去除犧牲層。所設計的元件尺寸為長260 μm，寬110 μm及1.5 μm的間隙。從實驗的結果可發現，此元件能在驅動電壓為10/0 V下，位移 90 nm且其共振頻率為36 kHz。由於金屬鎢栓(tungsten plugs)的結構遭受破壞，因此目前元件只能透過光學觀察的方式來驗證其邏輯功能。

This paper presents the design, fabrication and calibration of a novel MEMS logic gate that can perform Boolean algebra as well as logic devices composed of solid-state transistors. This MEMS logic gate design inherits all the advantages from MEMS switches and thus is expected to have more applications than MEMS switches. Unlike existing designs, the proposed design can perform either NAND gate or NOR gate functions using the same mechanical structure, but different electrical interconnects. Thus, this design can signiffically reduce the layout area consumption and improve the yield fabrication of devices. In order to accomplish those universal gates, the proposed design should fulfill three requirements on the fabrication process: two voltage levels carried on a suspended plate, metal-to-metal contact between shuttle electrodes and fixed electrodes, and a low process temperature (<400℃). Hence this study proposed two kinds of process designs to achieve the MEMS logic gate, including the in-house developed process design and the foundry service CMOS-MEMS process design. However, the residual stress in this fabricated device is substantial which could impair the functionality of the device. Therefore, a novel in situ film stress calibration method is proposed to assist the development of the in-house developed process. Also, different combinations of oxide-metal films and post-CMOS process are investigated to achieve a non-warping suspended structure layer in the foundry service CMOS-MEMS process. In the in-house developed process design, the fabricated device is 250 μm long, 100 μm wide and of 3.97 μm gap. Experimental results show that the device can operate at 25/-25 V and 100 Hz, and achieve the proposed logic functions. In addition, several properties of this device are experimentally evaluated, including power consumption, on/off resistance, lifetime and resonant frequency. In the foundry CMOS-MEMS process design, the experimental results show that this device can be actuated by 10/0 V with a moving distance 90 nm. The resonant frequency is measured at 36 kHz. Due to the damage of the tungsten plugs, the logic function can only be verified by its mechanical movements instead of electrical readouts for now.