标题: | 多晶矽奈米线环绕式闸极薄膜电晶体之研究 Study of Gate-All-Around Poly-Si Nanowire Thin Film Transistor |
作者: | 黄柏钧 Huang, Po-Chun 许钲宗 Sheu, Jeng-Tzong 材料科学与工程学系 |
关键字: | 薄膜电晶体;环绕式闸极;矽奈米线;TFT;GAA;Si nanowire |
公开日期: | 2011 |
摘要: | 在本论文中探讨了一些技术来达到在系统面板上对高效能的低温多晶矽薄膜电晶体的需求。主要的概念是利用多重闸极(multiple gate)的结构配合氨电浆(NH3 plasma)的处理来改善元件特性。本论文探讨了多晶矽奈米线环绕式闸极薄膜电晶体(gate-all-around polycrystalline silicon nanowire thin-film transistors)的特性。和传统的薄膜电晶体相比,提出的环绕式闸极薄膜电晶体对氨电浆处有更好的效率并展现出了优越的特性,如较低的临界电压(-0.38 V)、陡翘的次临界斜率(114 mV/dec)、高电流开关比(>108)、和较低的汲极引发能障降低效应(13 mV/V)。此外由于低温多晶矽薄膜电晶体本身材料的限制,元件和元件间的特性差异变的特别严重,而这也限制了其在系统面板上的应用。针对这个问题,本论文也探讨了多重闸极和多通道结构对元件变异性的影响。由实验结果发现除了闸极结构对变异性会有影响,结合增加通道的数目可以更进一步有效的降低元件间的电性差异。由本实验发现当利用环绕式闸极结构并配合16个以上的通道可以使元件特性有最低的标准差(临界电压和次临界斜率的最低标准差分别是30 mV和11.4 mV/dec)。此外,本研究也实现了有记忆体功能的SONOS (Silicon-Oxide -Nitride-Oxide-Silicon)型式的环绕式闸极薄膜电晶体。由于角落电场效应(corner effect), 提出的SONOS型式的环绕式闸极薄膜电晶体在记忆体的写入抺除特性上有良好的表现。其中在写入特性上,闸极电压16 V且操作时间16 μs下可以有1.27 V的临界电压变化。而在抺除特性上,可以在闸极电压-17 V且操作时间1 ms下可以有0.5 V的临界电压变化。 In this work, several techniques are studied to developed high-performance LTPS TFTs which is required for system-on-panel (SOP) applications. The concept is adopted the multiple gate, and NH3 plasma passivation to improve performance. We had investigated the characteristics of gate-all-around (GAA) polycrystalline silicon nanowire (NW) thin-film transistors (TFTs). Compare to conventional planar TFT, the GAA NW TFT exhibits the superior performance and more efficiency for NH3 plasma treatment. The proposal GAA NW TFT exhibits a great improvement in performance including lower threshold voltage (-0.38 V), a steeper sub-threshold swing (114 mV/dec), a higher On/Off current ratio (>108), and a virtual absence of drain-induced barrier lowing (13 mV/V). The device-to-device variation is a serious problem in LTPS TFT and its limits the design rule in SOP application. We also addressed the variation immunity of different multiple gate structure and multiple channel configuration. In this experiment, not only the gate configuration but also the presence of multiple channels efficiently reduced the variation in the electrical characteristics. The device adopted with surrounding gate and featuring up to 16 channel exhibits the best performance and minimized standard deviation (30 mV and 11.4 mV/dec of threshold voltage and subthreshold swing, respectively). Finally, the GAA SONOS TFT with memory function had been realized. Due to the presence of corner effect, the GAA SONOS TFT brings the advantage in programming and erasing characteristics. The fast programming (t = 10 μs, Vg = 16 V) and erasing (t = 1 ms, Vg = –17 V) achieved threshold voltage shifts of 1.27 and 0.6 V, respectively. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079418838 http://hdl.handle.net/11536/40798 |
显示于类别: | Thesis |