用於雙頻帶802.11a-802.11b無線網路系統之可程式增益放大器電路設計

Abstract

本篇論文主旨在藉由電路的設計及模擬，實現一個適用於雙頻帶802.11a-802.11b無線網路系統之可程式增益放大器，具有高頻寬，低雜訊，直流誤差補償，易於控制增益大小的優點。 此設計是採用四級差動放大器的架構來達到系統要求，增益範圍設計在0dB到60dB，最低增益步階為1dB。 在高增益的情況下等效輸入雜訊電壓Vn僅6.5nV/sqrtHZ，頻寬仍可達125MHz。 本論本中所提出的可程式增益放大器，是以安捷倫ADS軟體模擬，並以聯華電子0.18微米金氧半製程實現，此製程具有一層複晶矽和六層金屬。當操作在1.8伏特電源電壓時，整個晶片僅消耗3.73mW (含四級可程式增益放大器，相關偏壓電路及直流誤差消除電路等，不含3.3伏特的輸出驅動電路)，在除能的狀態下消耗3.6uW，晶片面積僅為0.01mm2。 本論文實現了一個低雜訊，高頻寬的可程式增益放大器。其可實現於一個低成本，低消耗功率及易於整合的相關應用。

The purpose of this thesis is to design and simulate a reliable circuit suit for Dual-Band 802.11a-802.11b wireless network system to realize a programmable gain amplifier, which includes the advantages of high-bandwidth, low-noise, DC-Offset-Cancellation feature and easy to control the gain setting. Using four Gain-Amplifier casecade architecture on circuit achieves the system requirement that the gain range is 0~60dB, with 1dB gain step. Input referred noise at high-gain mode is only 6.5nV/sqrtHZ, and bandwidth up to 125MHz. The proposed circuit simulates with Agilent ADS tool, and the circuit is implemented with UMC 01.8um 1P6M CMOS process. The verification values approaches to the simulation results. It consumes only 3.73mW from a 1.8V supply voltage (includes 4-stage Gain-Amplifier, related bias circuit and DC-Offset-Cancellation circuit; the 3.3V output drive circuit is not include). The consumption of power-down mode is 3.6uW and die occupies 0.01mm2. In sum, this work presents a low-noise and high-bandwidth PGA circuit for a low cost, low power, and high-integration solutions.