應用於低成本及高速化的多種類記憶體晶片系統之新型可程式化控制(n, k, m)編碼參數的錯誤更正編解碼器

Abstract

本篇論文使用新的錯誤更正碼的建構方式去實現了一個新型可程式化控制的錯誤更正編解碼器之架構，這個被提議的錯誤更正碼具有「單一位元的錯誤更正，單一位元組內有奇數位元的錯誤更正及單一位元組的錯誤偵測，兩個位元的錯誤偵測」之錯誤更正及偵測的能力，並命名為SEC-SoddEC-SBED-DED codes。 此外一個關鍵的重點是它很適合用於可程式化(n, k, m)編碼參數之控制，此處的n表示整個ECC編碼長度、k表示被編碼的資料長度、m表示被編碼的資料的寬度，因此這個被提議的SEC-SoddEC-SBED -DED codes具有非常彈性化的資料編碼長度及寬度，可進行任何的(n, k)系統體系上區塊編碼。 本篇論文主要的目的是利用這個被提議的錯誤更正碼，去完成一個具有高速化及低複雜度的可程式化之順向錯誤更正編碼與解碼電路，能符合多種類記憶晶片系統應用上所需的高性能、低成本及適當的可靠度之需求。 另外地，我們也提出了交錯式SEC-SoddEC-SBED-DED codes方法，可使得順向錯誤更正編解碼器具有多個位元組的錯誤更正及偵測的能力，大幅提高了整體錯誤控制系統的可靠度，進而可朝向更廣泛與多樣化的串列資料傳輸上的錯誤更正編碼之應用。

This paper utilizes new error-correcting-codes constructing approaches to present a new programmable control (n, k, m) error-correcting encoder-decoder architecture. The proposed ECC is named SEC-SoddEC-SBED-DED codes to have these capabilities of random Single bit Error Correction－Single odd-bit Error Correction within a single byte－Single Byte Error Detection－random Double bits Error Detection. An important key point is that the proposed error-correcting code/circuit (ECC) is very well to these programmable or variable (n, k, m) parameters, where n=an ECC codeword length, k=an encoded information length, m= data-I/O wide. In other words, the proposed SEC-SoddEC-SBED- DED code has a very flexible code-length and code-width to any type of a (n, k) systematic block-code without restriction. Main purpose of the thesis is to show that the proposed error-correcting codes can finish a high-speed, low-complexity, programmable forward ECC encoding and decoding circuits to meet the high-performance, low-cost and moderate reliability demands for various memory-chips system applications. In addition, we propose also interleaving SEC-SoddEC- SBED-DED codes for the FEC-codec system which reaches to multiple bytes error correcting-detecting accomplishment. Hence the reliability of whole error control system is enhanced in order to drive toward the wide varieties of serial error control coding systems applications.