溝槽型功率金氧半場效電晶體切換速率改善研究

Abstract

功率電晶體被廣泛用做高頻低壓( <200 V)開關模式電源轉換器的主要元件，功率電晶體的切換速率主要是由閘極電容充放電的動作決定，閘極-汲極電容愈大，電荷切換時間愈久，元件速度變慢。在高速元件的切換應用中，極低的閘極-汲極電荷與極低的導通電阻可減少切換損耗，並提升整體效率，以往在溝槽型功率電晶體有許多研究方法都是增加晶胞密度來降低導通電阻，但是閘極的寄生電容也因此變多了導致充放電速度變慢。本論文之研究主要是針對0.4微米溝槽式功率金氧半場效電晶體做探討，利用縮小溝槽寬度來降低高密度功率電晶體閘極-汲極電容，然而在晶圓的製作過程中，溝槽寬度受限於曝光顯影機台(I-line)能力，本研究利用既有的I-line 曝光顯影機台，在第一次罩幕蝕刻後，沉積一TEOS堆疊薄膜於第一次罩幕區域邊襯上，在第二次罩幕蝕刻時形成側壁間隔物，此側壁間隔物縮小了原本光罩定義溝槽蝕刻的區域，因此在溝槽蝕刻時有效縮小溝槽寬度至0.15 微米，另外P-N接面位置是可以使用離子佈植及回火技術作精確控制，由實驗結果顯示此方法的確有效降低溝槽寬度，並且降低了閘極-汲極電容。

Power MOSFETs are widely used as a switching device for high frequency and low voltage (<200 V) power converter. The switching rate depends on charging and discharging performance of the gate capacitor. Low gate - drain charge and low on-resistance can reduce switching power loss and thus improve the device performance. Many approaches have been developed to increase the unit cell density to reduce the on-resistance in trench type power MOSFETs, but the switching will become slower while the gate parasitic capacitance increases. This thesis presents the investigation on narrowing the trench width to reduce the gate - drain capacitance. For the sake of cost considerations, the i-line stepper was used for the wafer production process instead of deep-UV stepper, therefore the trench width was limited by the lithography resolution. After the first step of hard mask etching, a TEOS thin film was deposited on the edge of the hard mask region to form a sidewall spacer, which defined the second hard mask for bulk etching. The spacer could narrow the width of the etched trench to 0.15 □m. Combining precise control of ion implantation and furnace drive-in processes for the P-WELL region, optimization of the trench width and depth using the new hard mask approach can effective reduce the gate – drain capacitance, and thus the feedback capacitance of the MOSFET.