介面保護與雷射退火增進高效能N型鍺電晶體之研究

Abstract

隨著半導體元件尺寸的不斷縮微，並且符合目前邏輯電路與高效能場效電晶體的發展，高效能的金氧半互補式場效電晶體 (CMOSFET) 的研發是勢在必行的。當以矽 (Si) 為基板與二氧化矽（SiO2) 為介電材料的半導體元件發展到一個瓶頸時，為了符合未來尺寸的微縮與高效能電晶體與的趨勢，高介電系數材料與高載子遷移率材料的開發似乎是不二法門。但增加介電常數和減少元件厚度所伴隨而來的高漏電與如何整合這些高介電材料在新基板更是目前研究的主要議題。而目前許多高介電材料如HfO2、 Al2O3、 La2O3、 TiO2等都被廣泛的研究。除此之外，一些高電子遷移率的基板，如矽鍺 (SiGe)、鍺 (Ge) 與砷化鎵 (GaAs)等，再近幾年也都陸陸續續被提出一些相關的研究文件，然而如何成功的整合這些新材料與新基板應用於大型積體電路上依然是一個困難的課題。 因此，我們針對新材料與基板所產生的問題，開發出一系列和氧化鑭相關(La2O3-based)的高介電材料，其中包括了鑭化鋁氧化物(LaAlO3)、鑭化鈦氧化物(TiLaO)和二氧化鋯(ZrO2)。除此之外，我們也成功的研究出整合介面工程 (Interface engineering) 與高介電材料的方法，成功的運用在鍺基板與高介電材料之間沈積一層很薄的二氧化矽保護層來做出高性能的N型鍺互補式金氧半場效電晶體 (Ge nMOSFET)，不但在漏電上有大幅的降低，更改善了鍺基板介面的一些平帶電壓(Flatband Voltage)的不理想效應，大大的增進了電容密度，使等效氧化曾厚度(EOT)在鍺基板可以微縮到0.85奈米 並且得到了高的電子遷移率。最後，由於前面成功的實驗，我們再加以運用雷射退火(Laser Annealing)的方式，使電晶體的特性更進一步的改善。

The development of the high performance complementally metal-oxide-semiconductor field effect transistors (CMOSFET) is expected to be imperative as the semiconductor devices continuously decrease in size along with the development of current logical circuits and high performance MOSFET. However, the size reduction of the Si-substrate and silicon dioxide (SiO2)-dielectric-material-based semiconductor devices has come to a bottleneck due to their low carrier mobility and the lower dielectric permittivity constants (K=3.9), hence the development of materials with higher dielectric constant materials and higher carrier mobility is unavoidable. The high leakage currents accompanying the reduction of the thickness of the devices and the increase in the dielectric constants, and the integration of these high dielectric constant materials onto the new substrates have been the main subjects of the recent studies. The researches of high dielectric constant materials, such as HfO2, Al2O3, La2O3, and TiO2 have been studied for decades. Furthermore, high carrier mobility substrates, such as SiGe, Ge, and III-V compounds (GaAs), have been widely proposed in some recent research articles. Nevertheless, successful integration of high dielectric constant materials onto new substrates for the VLSI technology still proves to be quite a difficult issue. In order to overcome the problems of integrating the new high dielectric constant materials and the substrates, we used a series of Lanthanum Oxide (La2O3)-based high-□ materials such as LaAlO3, TiLaO and ZrO2. We had also studied the interface engineering and successfully fabricated high performance Ge nMOSFET by depositing an ultra thin SiO2 passivation layer between the Ge substrates and the high dielectric materials. Using the interface passivation not only reduces the electric leakages, but also improves the unwanted flat-band voltage (Vfb) shifts on the Ge substrates as well as the capacitance density, enabling the equivalent oxide thickness (EOT) to scale down to 0.85 nm with higher carrier mobility. Finally, we used the laser annealing (LA) method to further improve the transistor characteristics of the gate stack structures.