於鍺基板製作n+-p型二極體及n型金氧半場效電晶體之電性研究

Abstract

我們已經最佳化出在鍺基板上製作n+-p型二極體的熱製程，並且進一步地成功製造出在鍺基板上的n型金氧半場效電晶體。在我們一開始的二極體研究中，我們在光罩上設計不同大小的離子佈值區域之面積去觀察二極體的漏電路徑。藉由總漏電流為「面積漏電」(JA)和「邊界漏電」(JP)兩者所組成的觀念，我們可以定性地了解在對某種製程下的漏電，究竟是被「面積漏電」亦或是「邊界漏電」的分量所主導。除此之外，對於面積漏電和邊界漏電的定量萃取，也展現出和定性上所得的結果有一致的結論，並且我們發現，無論是否在活化前沉積一層SiO2，沿著離子佈值區域的邊長上之缺陷應該被消除掉，否則將會因嚴重的邊長漏電而導致反向漏電流的增加。然而，即使是這些缺陷被消除的非常好，邊長漏電對於總漏電的比例還是和我們離子佈值區域的大小有關。因此，當我們微縮電晶體的時候，這些沿著源極和汲極(S/D)的邊長分布之缺陷應該要被活化更好。另一方面，我們發現活化前所沉積的SiO2層的作用是減少Al和Ge間的接觸電阻。因此，較高的順偏電流和較好的汲極飽和電流(drain saturation current)可以被達成。 藉由利用前面所得的活化製程最佳化的結果，我們接下來以高介電參數之介電層Al2O3為閘極介電層，去製作出以鍺為基板的n型金氧半場效電晶體，並進一步地研究它們的電性。無論是汲極電流對閘極電壓(Id-Vg)、汲極電流對汲極電壓(Id-Vd)和電容對電壓(C-V)的特性，或者是一些電性參數，如：源極和汲極的電阻(source-drain resistance)、載子內擴散長度(dopant in-diffusion length)和次臨界擺幅(sub-threshold swing)也被萃取出來以了解元件的特性。雖然我們可以達到開關電流比(on-off ratio)對於汲極電流和源極電流分別為103和104，但是嚴重的源極和汲極的電阻仍被觀察到。 最後，我們考慮使用氮氫混合氣體退火(FGA)製程去改善高電阻的缺點。一些參數被萃取出來比較經過氮氫混合氣體退火前後的差異。結果顯示無論是源極和汲極的電阻或者通道電阻(channel resistance)皆可被改善很多。不幸地，二極體接面漏電變得難以控制並且大幅劣化我們的場效電晶體特性。確切的原因應該藉由進一步的物理分析來證實。

We had optimized the thermal processes to form n+-p junction on bulk Germanium and further succeeded in fabricating Ge nMOSFETs. At the beginning of our diode studies, we designed different areas of implantation region on our masks to observe the leakage paths. By the concept which states total junction leakage currents were composed of JA and JP, we could know that the leakage current for certain fabrication process was dominated by “area” or “perimeter” component qualitatively. Besides, an quantitative extraction of JA and JP also consisted with these qualitative results, and we found no matter if a capping layer SiO2 was deposited before annealing, it exhibited defects along the perimeter of implantation region should be eliminated well, or an increasing reverse current would appear due to a severe JP. However, the ratio of perimeter current to total leakage current was still dependent on the dimension of our implantation area even if the defects were activated very well. Hence, as shrinking the transistors, the defects along the perimeter of S/D should be activated better. In addition, we found the influence of capping layer SiO2 which was deposited just before activation was to reduce the contact resistance between Al and Ge. Accordingly, a higher forward current and a much improvement on drain saturation current could be achieved. By utilizing the results of optimization of the activation processes, we subsequently fabricated Ge nMOSFETs with Al2O3 as our high-k gate dielectric and further investigated their electrical performances. Not only Id-Vg, Id-Vd, and C-V performances, but also some electrical parameters, such as source-drain resistance, dopant in-diffusion length, and sub-threshold swing, were extracted to realize the device characteristics. Although we could achieve on-off ratios about 103 and 104 for drain and source currents, respectively, a severe source-drain resistance was also observed. Finally, we considered the forming gas annealing (FGA) process to improve the drawback. Some parameters were also extracted to compare together before and after FGA. It actually demonstrated not only source-drain resistance but also channel resistance could be much improved. Unfortunately, the junction leakage current became out of control and much degraded the electrical performances on our Ge nMOSFETs. The exact cause should be investigated by some further physical analysis.