使用倍數式延遲鎖相電路之非整數頻率合成器

Abstract

資料運算中時脈供應源有必要與其它系統是被整合在單一晶片上(on chip clock multiplication)，突波(spur)與相位雜訊(phase noise)，這些要素經常是影響量測品質的關鍵。一般整倍數延遲鎖相電路(MDLL，Multiply Delay Lock Loop)，參考時脈訊號重載(reload)的動作，達到清除擾動累積 (jitter accumulation)的功能。但此項功能卻有一代價要付出，參考訊號重載或是重整，造成時脈訊號有特定擾動(deterministic jitter)的產生，在時脈訊號的頻譜上會有明顯參考突波(reference spur)的發生，故使延遲鎖相電路的突波抑制將是本研究重點，而我們是如亂數把此特定擾動打散將有助於抑制突波。另一方面，為了使系統使用的頻譜的使用率相對於整倍數的頻率合成器比較高，以和差調變器來產生平均數為小數解析度的行為，並有非整數編程式的形態(fractional- N programmable)的特性達到之，如此般輸入參考頻率將不受限於調變訊號，給予系統有一高度調整性的設計，而非整倍數頻率合成器在目前電路系統上，主要是以非整倍數鎖相電路(fractional-N PLL)為主流，如何使擾動累積清除的特性，發揮於非整倍數頻率合成器，故發展非整倍數延遲鎖相電路。

參考時脈訊號重載如何實現於非整倍數延遲鎖相電路上，先要得知參考相位與時脈訊號相位的量化資訊，是否可正確重載參考訊號，否則將發生嚴重錯誤的相位偏差。為了推算那一特定時間內能作重載，我們將改進和差調變器，和差調變器的進位訊號(carry[k])可算出補數訊號(residue[k])，補數訊號就能反應參考相位與時脈訊號相位的量化誤差，分為三個部份，用於改變除數的和差調變器(ΣΔ1)，計算相位的累加器，經過一量化器(Q)，回授路徑上補數之和差調變器 (ΣΔ2) 。特點在於，加於用於改變除數的和差調變器之輸入的回授路徑，使補數訊號(residue[k])能用於避免相位偏差，以推算那一特定時間內能作重載參考時脈。補數訊號(residue[k])是反映參考相位與時脈訊號相位的量化資訊，將此訊號送給延遲線(delayline)，達到參考訊號重載的功能。參考訊號重載能打斷延遲線的相位雜訊的累積，雜訊模型將由一積分器模型變成離散時間上的相加，所以在設計迴路濾波器(loop filter)能以考慮和差調變器的量化雜訊與參考訊號雜訊為主。此非整倍數延遲鎖相電路架構用能用為非整倍數時脈產生器，壓抑頻帶內的相位雜訊(In band phase noise)，達到低雜訊的效果。

亂數把此特定擾動打散的方向下，我們提出較廣義的訊號重載架構，保存傳統倍數延遲鎖相電路的清除擾動累積的優點，以一組多相位產生器(multi-phase generator)，產生的多時脈相位重載於一組延遲線(delay line)上，訊號重載的方式將以數位控制器(digital controller)來安排，決定重載於時脈訊號的何時刻和時脈相位的位置。若以一個隨機亂數的方式來安排重載參考時脈訊號的順序，能有效抑制突波產生，定性上在頻譜上其明顯之突波單頻訊號將下降，下降程度能以馬可夫鏈(Markov chain)得之，溢出相位雜訊能用隨機過程定量之。上敘能以一實際例來說，多相位產生器以一組延遲線產生多相位時脈產生，並以N+ΔN周期，ΔN是一亂數方式，重載於另一組延遲線，以達到達到抑制突波，驗正溢出相位雜訊不會有太大的付出。

我們主要發展一新型非整倍數頻率合成器，非整倍數延遲鎖相電路，與突波抑制的延遲鎖相電路。除運用於本計畫相關的類比數位轉換(ADC)系統下，也可在其他具有非整倍數頻率合成器的系統

These days the clock generator integrated with other system is needed to realize high speed computation. Spurious tones and phase noise often play a critical role in measuring quality. Random jitter is significantly reduced in Multiplying Delay-Locked Loops (MDLL), phase realigning clock multipliers, compared to that in typical Phase-Locked Loops (PLL). This is performed by launching the reference edge directly into their voltage controlled oscillators (VCO) or their delayline. However, the timing mismatch in singal path to the detector as well as non-idealities of analog property in the circuits casuse a significant increase in deterministic jitter. So dealing with the spurious tone the same as deterministic jitter is this research topic. On the other hand, the channel efficiency of communication system used by the fractional-N frequency synthesizer is much higher than that used by the integer-N frequency synthesizer. The sigma delta modulator adopted in fractional- N frequency synthesizer achieves the resolution of fractional-N by generating the fractional number in average and have the property of programmable. Yet the frequency of the reference clock is not limited and not confined within the modulation signal, which gives greater design flexibility at the system level. Recently fractional- N frequency synthesizer mainly uses fractional- N frequency PLL to serve as the supply of the clock. How to reduce to phase noise contributed from jitter accumulation of the PLL/MDLL on commutation systems is the main point of our invention. The realization of the concept of the adjustment of the reference clock on fractional- N based MDLL is that, first to know quantized information compared between the reference clock and the divided clock, generated from divider having divider ratios modulated by the sigma delta modulator (ΣΔ) to achieve fractional – N resolution. Reload the reference clock correctly or not that cause serious problems of phase offset. We modify the sigma delta modulator (ΣΔ) to predict the signal of the residue (residue[k]), which is synchronized with the error compared between the reference clock and the divided clock. The modified sigma delta modulator (ΣΔ) consists of three parts, the sigma delta modulator changing the divider ratio, the accumulator counting the reference edge, and the residual sigma delta modulator on the feedback loop. The point is this feedback loop make the the residue (residue[k]) avoiding the phase offset to align the reference edge. The residue (residue[k]) is used to determine the time of the reload of the reference clock, and let the delay line has the ability of the alignment. Because of the elimination of jitter accumulation, quantization noise of the sigma delta modulator and the noise from the reference clock induced phase noise is the bottleneck in state-of the-art synthesizer design. Under this circumstance we propose a general form of MDLLs, which have the adjustment by reference clock, and can keep the advantage to prune away jitter accumulation. This general form composes of a multi-phase generator, a delay line, and the digital controller. The clock phases from the multi-phase generator can be reloaded in the delay line and the digital controller determines the allowance to reload the clock phase and the order of reload. If the order is random pattern, the spurs caused by the adjustment can attenuate effectively. The value of attenuation can be predicted by the theorem of Markov Chain. For example, the multi-phase generator implemented by a delay line which is rounded by delay cells use the order N+ΔN, ΔN is random variable, to inject the second delay line to reduce the spurs. The amount of the reduction of spurs and the phase increment are verified under both behavior simulation and math, and less than 6dB. Note that the invention is not limited to ADC system, but is applicable to other systems and integrated circuits that have low noise, fractional – N resolution of MDLL.