一個可做動態電壓/頻率調整且使用中繼器的匯流排電路設計

Abstract

本論文提出一使用嵌入式中繼器的匯流排電路，來降低全區域連接線時間延遲、功率及面積消耗，並且利用一個時脈檢測電路來觀察訊號雜訊的大小，依照檢測訊號的不同，我們可以分析出訊號是否適合在此電壓此頻率下工作。若不適合工作在此電壓或頻率之下，再決定是要調整電壓，或調整資料傳送的頻率，來使得資料能夠正確的傳輸。

在資料產生方面，使用偽隨機資料產生器來產生8筆並聯的偽隨機資料，並且同時產生一時脈訊號 (用來做時脈檢測)，觸發位置剛好切在資料的中間點，資料和時脈訊號同時經過傳輸距離為10mm的匯流排電路，再由時脈檢測電路來檢測訊號的雜訊大小。此晶片使用台積電 0.13 m RF CMOS 製程來實現。在1.2V的電源供應下，偽隨機資料產生器的功率損耗約1.36mW，傳輸線消耗功率約22.18mW (每條消耗功率約2.77mW)，檢測電路的功率消耗約9.75mW。

This thesis proposes a bus circuit using repeater insertion to reduce its power consumption and area. Moreover, we use a timing measurement circuit to estimate eye opening and jitter. According to the eye opening, we can determine if the supply voltage or the frequency is adequate for the task. If the supply voltage or the frequency disagrees with the task, we can dynamically change the supply voltage or the frequency to make the signal correctly transferred.

For the data generation, a pseudorandom binary sequence generator has been used to generate eight parallel outputs and a divider to generate a clock signal. The clock’s trigger location is at the middle of pseudorandom data. The data and the clock have been transferred to the bus circuit which is 10mm in length. Finally, we use a timing measurement circuit to estimate the jitter. This chip is implemented in TSMC 0.13um RF CMOS process. On a 1.2V power supply, the PRBS generator consumes 1.36mW, the global interconnects consume 22.18mW (each interconnect consumes 2.77mW), and the timing measurement circuit consumes 9.75mW.