以90奈米CMOS製程設計一應用於前瞻串列式連結收發機之超高速資料轉換器對

Abstract

本論文提出一組以聯電90nm CMOS Mixed-Mode製程設計製作之應用於前瞻串列式連結傳輸系統收發機之超高速資料轉換器對。該數位類比與類比數位轉換器之規格皆為每秒一百億次取樣率、四位元解析度。數位類比轉換器為電流導向的架構，且使用操作速度較快之電流式邏輯電路作為核心數位電路的設計。此種電流式邏輯除了適用於低電壓的操作環境之外，也可達到非常高速的切換能力並降低高速轉換中電源的抖動量。而其中較關鍵性的元件－開關輸出電流源使用疊接電流源電路，以提供在高頻時較高的輸出阻抗，使高頻操作的特性可以更好。另一方面，我們使用快閃式的架構來實現超高速類比數位轉換器。透過串接多級具備主動式負回授技術的前置放大器使比較器陣列具有超寬頻，與低功率的特點。而數位電路部份相同也採用電流式邏輯電路作設計。為了解決高速資料轉換器測試上的困難，我們加入一組可測試性電路並提供兩種測試模式，使實驗晶片可以進行全速運作下的動態參數以及眼圖的量測。晶片量測結果顯示，在全速運作的測試模式下，輸入一1.111GHz的弦波訊號，可得27.0 dB的訊號雜訊比以及25.9 dB的訊號雜訊失真比，對應到四位元的有效位元數。眼圖量測結果顯示此設計能提供達到每秒一百億位元的資料傳輸速率。在1V供應電源下，整個測試晶片共消耗約322.8 mW之功率。

This thesis presents a very high speed data converter pair in UMC 90nm CMOS Mixed-Mode technology for the design of the transceivers of advanced serial links. The digital-to-analog (DAC) and the analog-to-digital (ADC) converters achieve a 10GS/s sampling rate and 4-bit resolution. The DAC uses the current-steering architecture. The digital circuitry is implemented with the current mode logic (CML) gates which have faster switching. The CML gates not only have less gate delays, but also are suitable for low voltage operation. In addition, they alleviate the issue of severe power-ground bouncing. We also applied the switched cascode current source (SCCS) to provide a higher output impedance at higher frequencies. The proposed ADC is a flash type ADC. The very wide bandwidth and low power comparators were realized by cascading multi-stage active negative feedback pre-amplifiers. To address the difficulty of testing the data converters at the rated 10GS/s, we added the design-for-testability (DfT) circuitry which provides two test modes including the at-speed test mode and the eye diagram mode. The measurement results of the test chip show that the data converter pair achieves an SNR of 27.0 dB and an SNDR of 25.9 dB with the 1.111GHz sinusoidal inputs in the at-speed test mode. It corresponds to an ENOB of 4.0 bits. The measured eye diagrams show that the data converter pair can provide a data rate up to 10Gbps. The test chip including the DfT circuitry consumes 322.8 mW from a 1V supply.