使用金氧半導體基板正偏壓設計的射頻高輸出功率放大器

Abstract

本篇論文主旨在設計一個可供長距離傳輸的高輸出功率的射頻放大器，其規格設定在 FCC 15.247 . 此設計是強調用基板正偏壓來減少所須金氣半導體的size , 使output stage 的輸入端的閘極的寄生電容下降，進而使driving stage能傳遞更大的輸出信號進入output stage. 另外為了兼顧線性度與效率，此電路設計第一級操作在class-A，第二級操作在class-AB. 而加上differential+cascode架構來增加輸出功率及避免閘極-汲極breakdown問題，另外以穩定加強電路來加強高低頻的穩定，使電路能達到操作時無條件穩定。 此設計的晶片是使用標準點25微米1P5M互補式金氧半導體製程。此晶片在量測過程中完全沒有振盪現象發生。實際量測此晶片在操作溫度26.2˚C、1.9GHz的頻率時，輸入信號功率為0dBm情況下，能提供25.3 dBm 的輸出功率，同時有17.51%的效率,而1dB compression gain (P1dB)是-9dBm, Adjacent channel power ratio(ACPR)在GSM(1.8GHz) 標準信號輸入下，在400kHz的頻寬下的ACPR 是-43.07dBc。

This thesis is proposed for designing a high-output-power RF CMOS power amplifier using MOS devices with positive substrate bias. This design is targeted on the standard of FCC 15.247. The MOS devise with positive substrate bias was used to reduce the devices size and relative parasitic capacitance. Furthermore, it’s helped that the driver stage can deliver large enough signal to output stage and improve the efficiency. To consider the linearity and efficiency, the input stage operates in class-A and output stage operates in class-AB. The differential with cascade topology is used to alleviate the gate-drain breakdown phenomenon. Besides, stability enhanced circuits are used to ensure that the design can operate in unconditional stable. This chip is fabricated in a standard 0.25μm single-poly-five-metal CMOS process. There are no oscillated phenomenon during experiment. Experimental results showed this chip can provide 25.3 dBm output power with 17.51% PAE at input power equal 0dBm at 26.2˚C. The 1dB compression gain is -9 dBm and the ACPR is -43.07dBc at 400kHz frequency when used GSM(1.8GHz) modulated signal as input.