適用於IEEE802.11a接收機之差異積分調變CMOS頻率合成器設計

Abstract

本篇論文主旨在於設計可工作於1.8V直流電壓且以全積體化互補式金半導體0.18-um為製程，適用於IEEE802.11a 接收機之差異積分調變分數型頻率合成器。此頻率合成器在5.12GHz~5.376GHz之頻率合成範圍內可以提供16Hz之頻率解析度，並且具有6us之快速鎖頻與低分數突波的特性。所設計的頻率合成器電路包含壓控震盪器(Voltage Controlled Oscillator)、相位/頻頻比較器(Phase-Frequency Detector)、多模數除頻器(multi-modulus divider)、電荷充放電濾波器(Charge-Pump filter)以及三階之差異積分調變器。 電壓控制振盪器由負電阻，螺旋型電感和P/N接面可變電容所組成，振盪器的輸出頻率可經由可變電容調整，經設計於控制電壓1.8V內，振盪器輸出頻率範圍可從4.88GHz到5.436GHz。 在前置除頻器(prescaler)方面，為了能達到在高速操作並且低耗電的目標，故採用pseudo-NMOS搭配TSPC型式的除法器來完成。至於多模數除頻器，可除頻倍數從16 到 31。整個除頻器經測量最高可工作在5.9GHz。相位/頻率偵測器是比較外部輸入參考信號與內部除頻後信號的相位/頻率差，產生充電UP和放電DN的數位信號，此數位信號會透過電荷充放電轉成類比訊號，透過三階低通濾波器變成近似 dc 的類比連續信號以控制壓控震盪器。 除以上所述電路之外，此頻率合成器亦整合一個全數位管線化，以多級雜訊整形為架構之三階差異積分調變器，藉由此差異積分調變器的雜訊整形技術來降低由除數控制訊號所產生的相位雜訊，此差異積分調變器製作於可編程邏輯程式元件(FPGA)。經測量此差異積分調變器能達到60dB雜訊整形的能力，此外對調變器輸出取樣2^18筆資料平均後，其分數的產生精確度可達到99.999％。 此頻率合成器使用是採用UMC 0.18um CMOS 1P6M製程並操作在1.8V的直流電壓。包含pads的晶片面積為2500um*2500um，總功率消耗小於49毫瓦。

This thesis presents the design of a fully integrated CMOS delta-sigma (ΔΣ) fractional-N frequency synthesizer with quadrature phase outputs intended for the local oscillator in WLAN 802.11a system using 0.18-um CMOS technology and 1.8-V single power supply. The proposed synthesizer can provide 16Hz frequency resolution within synthesized frequency range from 5.120GHz to 5.376GHz and meanwhile achieve fast locking time which is no more than 6us. Furthermore, its phase noise also improved by ΔΣ Fractional-N technology. The designed ΔΣ fractional-N synthesizer is composed of a LC-tuned voltage-control oscillator (VCO), a divide-by-16 prescaler, a multi-modulus divider (MMD), a phase-frequency detector (PFD), a charge pump with third-order passive loop filter and third-order ΔΣ modulator. The VCO is an LC-tuned negative-resistance oscillator. Its output frequency can be adjusted by P+/N-well varactor and can be varied from 4.88 to 5.436 GHz at 1.8-V power supply. For low power and high speed consideration, the feedback high-speed divide-by-16 prescaler is composed of a pseudo-NMOS type divider and a True-Single-Phase-Clock (TSPC) based frequency divider. The multi-modulus divider has a frequency divide ratio, ranging from 16 to 31. The highest input-frequency of the frequency divider is 5.9GHz. The charge pump receives the UP and DN signals from the PFD and output successive dc-like analog signal for the VCO through the third-order passive loop filter. The third-order all-digital ΔΣ MASH modulator is implemented in FPGA which operates together with the multi-modulus divider that is be used in this frequency synthesizer. To achieve the desired operation frequency range (16 MHz or higher) while providing low-power dissipation and small area. The pipelining technique was utilized in the design. The third-order MASH modulator measurement results confirm the 60 dB per decade increase in the spectrum, validating the third-order noise shaping. Furthermore, for samples of modulator output the fraction was represented to an accuracy of 99.999％. The pipelining technique was utilized in the design The ΔΣ fractional-N frequency synthesizer has been fabricated with UMC 0.18-um CMOS (1P6M) 1.8V technology except for the ΔΣ modulator. The total chip area is 2500um X 2500um. The total power consumption is 49mW from a single 1.8V supply.