REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY

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DC Field	Value	Language
dc.contributor.author	WANG, JJ	en_US
dc.contributor.author	JEN, CW	en_US
dc.date.accessioned	2014-12-08T15:05:35Z	-
dc.date.available	2014-12-08T15:05:35Z	-
dc.date.issued	1990-05-01	en_US
dc.identifier.issn	0143-7062	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4117	-
dc.language.iso	en_US	en_US
dc.title	REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY	en_US
dc.type	Article	en_US
dc.identifier.journal	IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES	en_US
dc.citation.volume	137	en_US
dc.citation.issue	3	en_US
dc.citation.spage	218	en_US
dc.citation.epage	226	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1990DC36000007	-
dc.citation.woscount	1	-
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