REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY

標題:	REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY
作者:	WANG, JJ JEN, CW 交大名義發表電控工程研究所 National Chiao Tung University Institute of Electrical and Control Engineering
公開日期:	1-May-1990
URI:	http://hdl.handle.net/11536/4117
ISSN:	0143-7062
期刊:	IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES
Volume:	137
Issue:	3
起始頁:	218
結束頁:	226
Appears in Collections:	Articles

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