管線式快速傅立葉轉換處理器之設計與實現

Abstract

本文對使用在4096點基數2 管線式快速傅立葉轉換及反快速傅立葉轉換處理器之儲存旋轉因數唯讀記憶體，提出減少其硬體成本之設計架構，實現的方法，主要是結合投影函數法及查表法，依此法設計，儲存旋轉因數唯讀記憶體之硬體成本，只需要682字元，與理論分析需要14337字元相較，可減少95.24%。 此外，本文亦提出新的高訊雜比定點數設計架構，所採用的設計方法，是將管線式結構，每一級處理運算單元的輸出，分成數個區域，然後以每一分區的最大值分別對該分區作正規化，在儲存旋轉因數唯讀記憶體與管線式資料路徑採用16位元定點數的情況下，4096點管線式快速傅立葉轉換處理器之平均訊雜比為76.68dB。

In this thesis, a novel architecture of reducing the hardware cost to the ROM stored the twiddle factor used in a pipelined 4096-point radix-2 fast Fourier transform (FFT) /IFFT processor is presented. The proposed method mainly combines the mapping function and the lookup table. Based on this design method, the hardware complexity of the ROM stored twiddle factor only demands 682 words. Compared with the hardware complexity that demands 14337 words in theory, it is reduced up to 95.24%. Moreover, a novel architecture of the high signal-to-noise ratio (SNR) is also presented. The adopted design method divides the output of each pipelined butterfly process unit into several sections and then separately normalizes them with different normalized bases according to the maximum corresponding to each section. Under the limitation of both twiddle factor ROMs and pipelined data paths that are adopted fixed point design with 16-bit word length, the SNR of the output of the 4096-point pipelined FFT is 76.68dB.