對於利用氮化矽局部電荷儲存之快閃記憶元件可靠度問題的探討

Abstract

在本論文中，我們針對以氮化矽(Si3N4)局部電荷儲存(localized charge storage)原理為快閃記憶元件之可靠度問題作了深入的研究。雖然此元件利用介電層缺陷(trap)為電荷儲存媒介以及以一較厚的穿隧氧化層(tunnel oxide)來提昇其電荷保存能力，我們仍觀察到該能力在元件經過重複的資料寫入╱抹除(program/erase)操作後大為衰退。研究後發現在寫入╱抹除過程中，於穿隧氧化層所產生的缺陷扮演了關鍵的角色。對一處於寫入狀態(program state)的記憶細胞而言，其臨界電壓(threshold voltage)的下降肇因於其儲存於氮化矽缺陷中的電子經由Frenkel-Poole放射機制到達氮化矽導帶，並藉由穿隧氧化層缺陷而逃逸。此外，部分的介面缺陷(interface state)在高溫烘烤測試後會逸失，此效應亦為臨界電壓下降的原因。對一處於抹除狀態(erase state)的記憶細胞而言，其臨界電壓卻隨著時間而漸增。這是由於穿隧氧化層中存有正電荷。這些正電荷隨時間逐漸脫離穿隧氧化層而導致所儲存的淨負電荷增加，並形成臨界電壓的正漂移。此外，當讀取儲存資料時，記憶細胞的閘極及汲極將被施予高偏壓。這些正電荷能增強通道電子或通道熱電子穿隧進入氮化矽層的機率而引發讀取擾動(read disturb)。我們亦發現，寫入及抹除操作後所引發的介面缺陷以及暫態基底電流(transient substrate current)的增量是該元件資料保存能力的良好指標。上述現象皆與電荷沿垂直於閘極介電層方向運動有關。但對於一過度抹除之記憶細胞而言，儲存的過剩正電荷易沿著氮化矽層橫向移動。此機制將導致通道短縮效應而使該記憶細胞之臨界電壓隨時間而下降。最後我們亦探討抹除速度退化的原因。我們發現在一近乎穿擊導通(punch-through)的記憶細胞中，鄰接接面的偏壓會調變熱電洞注入效率，抹除速度因而改變。此外當儲存電子愈靠近通道中央時愈難抹除。這些遠端電子較易產生於一個鄰接位元已為寫入狀態的記憶細胞中，特別是一個經過多次寫入╱抹除操作後的記憶細胞。

Reliability issues in a trapping nitride, localized charge storage flash memory cell are comprehensively investigated in this dissertation. Though the use of a thick bottom oxide and trapping storage concept provides excellent intrinsic charge retention, data loss is found after program/erase (P/E) cycling. Our study shows that trap generation in the bottom oxide during P/E cycling plays a central role. Vt loss in a program-state cell is due to the escape of trapped electrons in the nitride via Frenkel-Poole emission and subsequent oxide trap-assisted tunneling. Interface state annihilation during high-temperature baking would be another source of the observed Vt loss. Vt drift-up in an erase-state cell is the outcome of the tunnel detrapping of cycling-induced positive oxide charges. Furthermore, these positive oxide charges could enhance channel electron tunnel injection and channel-hot-electron injection into the nitride during read operation and thus cause read disturb. Stress-induced interface state growth and transient substrate current are good indicators of cell’s retentivity. All the above regard the charge transport along the vertical direction. On the other hand, lateral migration of excess holes in the trapping nitride dominates the Vt loss in an over-erased cell. Finally, erase speed degradation is studied. It is found that neighboring junction bias would suppress the hot-hole injection efficiency in a nearly punch-through cell. Besides, a cell is hard-to-erase if more electrons reside in the central channel region. Those far electrons are prone to be injected as its neighboring bit is programmed or after P/E cycling.