二次電子電壓對比應用於摻雜分佈與缺陷定位之研究

Abstract

本論文研究以二次電子電壓對比(secondary electron potential contrast, SEPC)應用於半導體之缺陷檢測與摻雜分佈觀察，利用SEPC來分析元件的電性特性。論文的第一部分是利用SEPC來定位互補式金氧半場效電晶體(complementary metal oxide semiconductor, CMOS)中的各種漏電或高阻值現象，應用於金氧半場效電晶體中的各節點可分為四類，如gate node、p+/n-well node、n+/p-well node、well nodes，傳統上都將入射電子束電壓(primary electron energy)設在1 keV，然後利用電壓對比的明暗效果來分辨是否有電晶體閘極氧化層崩潰與金屬導線斷路缺陷，然而簡略的明暗二分法卻無法將金氧半場效電晶體中的四類節點都妥善分類，譬如p+/n-well node和well nodes在電壓對比都是亮的，因此缺陷像p+/n-well node漏電就沒有辦法跟well nodes分辨開來，因此傳統的使用條件有其不完美面。經由深入研究我們發現電壓對比的來源是入射電子束與試片的交互作用致使試片表面產生正或負的電荷，文獻中慣用的入射電子束電壓1 keV就會產生正的電荷累積於試片表面，正的表面電荷對於p+/n-well node屬於順向偏壓，電荷都導入well，是故在此條件下無法分辨p+/n-well node與well nodes。本研究提出以入射電子束電壓5 keV為條件，嘗試將試片表面改為負的電荷累積，因此p+/n-well node處於反向偏壓而得以跟well nodes做出區分。本研究並以此新的條件應用於一個真實案例，實驗顯示傳統的1 keV條件無法分辨出缺陷位置，然而5 keV條件卻可以成功定位出缺陷位置，補足了傳統方法的不完美。 論文的第二部分是利用二次電子電壓對比來觀察pn二極體的摻雜分佈，相關文獻很早就發現此一現象，而且普遍認為二極體中空乏區的內建電場是電壓對比的來源，本研究也利用此一特性成功的在一個真實案例確認了p-well光罩偏移造成p+/n-well node的漏電。然而此一摻雜對比並不是很容易可以觀察的到，文獻研究顯示試片處理過程在表面所產生的破壞層是阻礙對比觀察的主要原因，這個部分也大大的阻礙了此一方法的應用，為了增強摻雜對比使其可以重複顯現，首先研究不同試片處理方法對於摻雜對比的影響，進而以微探針將p+/n-well二極體置於反向偏壓的狀態，實驗結果顯示在加電壓之前完全沒有摻雜對比可以觀察，在加電壓之後摻雜對比可以有效回復，並且在低濃度摻雜區域p-區域(lightly-doped drain region, LDD)也可以清楚顯現，顯示此條件有很好的解析度與實用性。本研究將摻雜對比影像數位化，將摻雜對比轉化成電壓尺度進行一維與二維的元件物理分析，成功量測出空乏區寬度(depletion width)與電性接面深度(electrical junction depth)，並與模擬結果比對討論。最後將此微探針增強對比設置應用於一個真實的電流鏡失效案例，成功判定p-well光罩的偏移造成電流鏡的失效原因，精確量出光罩偏移量，並且經過量產實驗確認偏移量無誤。 總結，本論文經由SEPC，並且利用最簡便可行的實驗設置，在缺陷定位上補足傳統方法的不完美，成功的將CMOS中的各節點妥善辨別。在摻雜分佈觀察上利用微探針偏壓方式回復消失的摻雜對比，並且經由影像數位化的過程成功的量測出空乏區寬度與電性接面深度，為未來固態元件摻雜分佈的研究提供了一個簡便可行的方法。

This study investigates the defect isolation and dopant profiling using secondary electron potential contrast (SEPC). A novel primary electron energy adjustment method is proposed to remedy the imperfections in traditional SEPC method, which uses fixed primary electron energy. For dopant profiling, a novel in situ nano-probe biasing is applied to enhance the SEPC signal, restoring the missing dopant contrast successfully. First author discusses the application of SEPC is applied to investigate the leakage and high resistance in a metal oxide semiconductor field effect transistor (MOSFET). The contact nodes in an MOSFET can be classified into four categories: the polysilicon gate node, p+/n-well node, n+/p-well node, and, well nodes. Most studies set primary electron beam energy (EPE) at 1 keV and used potential contrast to identify the gate oxide rupture and continuity failures. However, the bright and dark contrast of samples cannot distinguish these four nodes types well. For instance, the contrast of a p+/n-well node and well nodes is bright in scanning electron microscope (SEM). However, a leaky p+/n-well node exhibits the same brightness as the well nodes, an insufficiency of the EPE 1 keV condition for identifying p+/n-well nodes and well nodes. Previous studies indicate that the contrast of SEPC arises from the surface charging effect, which is initiated by the interactions between the primary electron beam and sample. The EPE 1 keV condition results in the positive charging on the sample. Positive charging will set the p+/n-well node in forward bias and leak positive charges into well nodes. Thus, the EPE 1 keV condition cannot be used to distinguish the p+/n-well node and well nodes. This can be solved by setting the p+/n-well node in reverse bias. This study increases the EPE to 5 keV to reverse surface charging from positive to negative. Experimental results demonstrate that the 1 keV and 5 keV EPE conditions can be used to identify these four nodes. Finally, the analytical method was applied to a real failure case and no abnormality under the conventional EPE=1 keV condition was observed. However, the proposed EPE=5 keV can isolate a defect successfully and complete the imperfect conventional method. The second part of this study discusses the application of SEPC to diode dopant profiling. Since 1967, researchers have observed dopant contrast in SEM image. The dopant contrast arises from built-in potential across the diode. This study also uses this property to identify a p+/n-well junction leakage path in a static random access memory (SRAM). However, for a small bandgap material like silicon, the built-in voltage is as small as 1.12 eV. Dopant contrast is weak and, in the worse case, no contrast is observable. The surface-damaged layer generated by sample preparation is believed to be the cause of dopant contrast reduction, inhibiting the application of SEPC to the integrated circuit (IC) failure analysis. For SEPC enhancement, this study studied the contrast effect under different sample preparation methods. By triggering the diode in the reverse bias condition through in situ nano-probe biasing, that dopant contrast can be restored. The SEPC image was digitalized and quantified for conversion of image contrast to the voltage scale, allowing the identification of the depletion region and electrical junction. The overlap length between the poly silicon gate and p+ region is also depicted by the two-dimensional (2D) imaging. The proposed method can maintain stable voltage conditions in the junction, facilitating the inspection of dopant area by SEM, and the development of an efficient method for examining dopant areas. Experimental results also confirmed the method has promising application in site-specific junction inspection. Finally, the novel method was applied to identified the failure cause of a current mirror mismatch. The inspection method successfully identified a 0.4 µm p-well layer misalignment caused by the mismatch. The experimental split also confirmed that a p-well misalignment exceeding 0.4 µm will cause failure.