以路徑方式將双端邏輯元件的方位做最佳化處理

Abstract

在現今的超大型積體電路設計中，減少總體繞線的長度是其設計流程中很要的一環。根據我們的觀察，從現有的商業軟體所設計出來的結果，其中仍有很多的雙端邏輯元件可以在不更改其本身的座標下，進一步地做鏡射的動作，來使得總體訊號繞線的長度能被縮短，且連帶地可以避免訊號交錯繞線的現象產生。因此我們提出了一種架構在以路徑的方式，利用重力吸引點的機制來改善現有的電路總繞線長度。此外，我們還提供了一種可以跟商用軟體連結的平台，此平台可以將我們所提出的方法輕易地跟商用軟體連結，以改善現有的設計流程。根據工業界實際案例的實驗結果顯示，我們的方法及平台確實可以有效地改善實體晶片的最終繞線長度。目前此一方法及平台已應用於金麗科技1GHz的實體化設計流程中。

In an IC cell-based design flow, reducing wire length is one of the purposes in the physical design stage. According to our observation, there are a lot of standard cells can be further mirrored to decrease the routing length, without impacting the original placed design. It is desirable to implement the optimization of orientation before or after the placement stage with a feature of single input and single output, which is further advantageous in avoiding wire crossing. The present invention relates to a method for determining orientation of a 2-pin logic cell, and more particularly to a method for determining an optimal orientation of a 2-pin logic cell placed in a signal chain path. We provide a path-based optimization methodology that can be linked with the physical design flow, and this will actually help the current commercial CAD tool to improve the final routing length. A number of real design cases are experimented to illustrate the effectiveness of the proposed methodology, and this method is already applied in the RDC 1GHz CPU physical implementation flow.