非揮發性記憶體的儲存電荷的空間分佈對元件特性的影響

Abstract

在本論文中，探討了非揮發性記憶體的儲存電荷的空間分佈對元件特性的影響。根據模擬的結果，調變臨界電壓(Vt)和調變閘極引發汲極漏電流(GIDL)是與電荷儲存的位置有關。當電荷儲存在通道中央的上方位置時，整個次臨界曲線會向右移，這是由於負電荷在捕陷電荷層的正中央會造成通道區域的電子位障上升。當電荷儲存在通道的上方並且靠近汲極的接面時，只有上半部份的次臨界曲線會向右移。這是因為通道區域中的電子位障被汲極電壓稍微地拉低了，所以下半部份的次臨界曲線不會移動，但是電子位障仍然不夠低，不足以讓電子完全地導通，所以上半部份的次臨界曲線會向右移。再來，當電荷儲存的位置正好在汲極接面的正上方時，閘極引發汲極漏電流會大量地增加。這是因為在閘極和汲極間的垂直電場變強了，所以閘極引發汲極漏電流會上升。長通道元件和短通道元件有相似的儲存電荷的空間分佈對元件特性的影響。 此外，我們證實在N型通道的多晶矽/氧化鋁/氧化鉿/氧化矽/矽(SAHOS)記憶體元件上單一位元胞中可以有三位元的記憶體特性。為了增加水平方向上的電荷儲存空間，我們把捕陷電荷層延伸到側壁空間層的底下。結合調變臨界電壓、調變正向讀取的閘極引發汲極漏電流以及調變反向讀取的閘極引發汲極漏電流，這些記憶體元件可以有三位元的操作。這些元件中，源極/汲極與閘極重疊的結構顯示出比非重疊的結構有較好的記憶體性能。在源極/汲極與閘極重疊的元件上，臨界電壓可以位移產生7V的記憶窗口，並且在外插到十年線後仍擁有良好的儲存資料持久性。此外，在105次寫入/抹除之後，此記憶體元件在調變臨界電壓上仍維持良好的性能。當此記憶體元件被運用在NOR型的非揮發性記憶體的陣列結構中，干擾效應對於臨界電壓來說是可以忽略的。閘極引發汲極漏電流可以在調變後產生約100倍大小的差異，但是沒有良好的儲存資料持久性，也沒有良好的耐操度。因為電荷是儲存在靠近側壁空間的角落，所以「水平電荷遷移」和增加電荷流失速率的缺陷都是造成沒有良好的儲存資料持久性的原因。而沒有良好的耐操度的可能原因是在每一次的寫入/抹除之後，儲存電荷的空間分佈改變了。對元件的可靠度來說，汲極的干擾效應對於閘極引發汲極漏電流是個問題。

In this thesis, the effects of spatial distribution of the stored-charge on device characteristics of non-volatile memory are evaluated. According to the simulated results, the modulation of the threshold voltage (Vt) and the modulation of the Gate-Induced-Drain-Leakage (GIDL) are related to the stored-charge positions. When the charges are stored at the position which is above the channel center, the whole subthresthold curve is moved to the right because of the negative charges stored at the center of the trapping layer resulting in a raise of the electron barrier of the channel region. When the charges are stored at the position which is above the channel and near the drain junction, only the upper half subthresthold curve is moved to the right. Because the electron barrier of the channel region is slightly dragged down by the drain voltage, the lower half subthreshold curve keeps. However, the electron barrier is not low enough to allow complete electron conduction, so the upper half subthresthold curve is moved to the right. Next, when the charges are stored just above the drain junction, the GIDL current increase largely. Because the vertical electric field between the gate and the drain is enhanced and then results in larger GIDL current. Both the long channel device and the short channel device have the similar effects of stored-charge distribution on device characteristics. Moreover, the 3-bit per cell memory characteristics are demonstrated on the n-channel poly-Si/Al2O3/HfO2/SiO2/Si (SAHOS) memory device. In order to increase lateral charge storage space, the HfO2 charge trapping layer extends to the underneath of the spacer. The 3-bit operations of these memory devices are demonstrated by combining the Vt modulation, the GIDL current modulation on forward read, and the GIDL current modulation on reverse read. The devices with the S/D-to-gate overlap structure show better memory performances than those with S/D-to-gate non-overlap structure. For the devices with the S/D-to-gate overlap structure, the Vt can shift with large memory window of 7V, and shows good 10-year extrapolated charge retention. Moreover, high endurance after 105 P/E cycles is exhibited on the Vt modulation. The disturbance effects of the Vt are negligible when this memory device is implemented by the NOR array architecture. The GIDL current can be modulated by about two orders of magnitude, but it shows poor retention and poor endurance. Because the stored charges are near the corner of the spacer, poor retention is due to “lateral charge migration” and the defects which enhance charge loss rate. The poor endurance is possible as a result of the change of the stored charges distribution after every P/E cycle. In addition, the drain disturbance on the GIDL is also an issue for device reliability.