新式雙閘極複晶矽奈米線薄膜電晶體與記憶體元件

Abstract

在本篇研究論文中，我們構思並成功地驗證一種簡易且具經濟效益的製作流程。此技術無需借助昂貴的微影設備與製程，即可製作出新式奈米線通道的薄膜電晶體。此技術運用一獨特的二階段乾式蝕刻技巧，可在一閘電極的兩側形成奈米極尺寸孔洞，並在沉積一矽膜將其填滿後，利用異向性蝕刻，自我對準地形成奈米線通道。運用此流程，可完成具有獨立雙閘極奈米線電晶體結構，在電性分析上可賦予更有彈性的操作模式，也可讓吾人針對各種操作模式進行比較與分析。我們也加入二氧化矽-氮化矽-二氧化矽(ONO)堆疊薄膜作為閘極介電層，及利用原生摻雜複晶矽作為源極/汲極(in situ doped source/drain)的技巧，可以有效提升閘極控制能力並且改善元件特性。基於此結構製作的記憶體元件，其特性上在具有更多彈性的雙閘極操作下，可提升元件基本電性及寫入/抹除速度。

In this thesis, a simple and cost-effective method for fabricating poly-Si nanowire (NW) thin film transistor (TFT) without the necessity of advanced lithography tools is proposed and demonstrated. In this scheme, a unique two-step etching is developed to form nano cavities at the sidewalls of an electrode. After filling the cavities with a Si film, an anisotropic etch is subsequently performed to define the NW structures in a self-aligned manner. With the proposed scheme, independent double-gated NW devices could be constructed. With such configuration, more flexibility in device operation could be provided. Characteristics of different operation mode are compared and analyzed. With the implementation of oxide-nitride-oxide (ONO) gate dielectrics and in-situ doped source/drain (S/D), dramatic improvements in device characteristics can be achieved. Based on the proposed scheme, NW TFT-SONOS memory devices were also fabricated and characterized. The two independent gates are shown to increase the flexibility and improve the programming/erasing efficiency.