氟化製程應用於金氧半場效電晶體鈍化層之特性與研究

Abstract

根據2008 ITRS PIDS Meeting所訂出最新金氧半場效電晶體之閘極奈米尺寸的演變趨勢，因受到新穎閘極材料無法持續之前最低可容忍漏電流規範，使得高效能和低功率應用的奈米微電子元件需延緩三或五個製程世代，本文中提出與現有製程具高度匹配性的四氟化碳電漿處理(CF4 plasma treatment)技術，利用氟化矽玻璃(FSG)當n型金氧半場效電晶體鈍化層的製程，在最後Sintering修補金屬界面斷鍵過程中，使氟原子有效擴散至高介電閘極本體和通道界面處，實驗結果顯示元件的電特性和可靠度可藉由通入適量的CF4氣體達到明顯的改善，因此可改善遷移率衰退以提昇驅動電流表現、較低次臨界擺幅和閘極漏電流、閘極引起汲極漏電流有明顯降低輸出等。 此外也分析可靠度劣化程度，在正偏壓-溫度應力(PBTS)和熱載子應力(HCS)可靠度特性上都有改善的效果，觀察到在電壓應力破壞下，均有較小的臨界電壓的偏移、較少的本體電子捕捉與界面狀態密度改變而引起元件的不穩定性，且在正電壓應力(PBS)與熱載子應力比較之下，熱載子應力造成的可靠度衰減相較於正電壓應力有顯著嚴重趨勢。這些元件電特性獲得改善及具有高度穩定性的可靠度呈現，造成的原因是來自於氟原子併入高介電閘極主體以及閘極層與通道界面間，不僅僅可減少界面狀態的懸空鍵結(interface dangling bond)和較低界面狀態產生，且進一步有效減少高介電閘極主體電荷捕捉情形。 最後在應力測試後再進行回復(relaxation)的行為，可分離HCS是由cold和hot載子兩個成份構成熱載子應力引起臨界電壓的偏移效應，其中cold載子具有逃逸(de-trapping)特性而hot載子會殘留在介電層形成永久傷害，不管在PBS或是HCS的回復行為，明顯觀察到氟化鈍化層元件有較少載子捕捉情形(應力下)及較高逃逸能障使得有較少逃逸現象產生(回復下)，這與先前討論Frenkel-Poole傳導機制，其比一般鈍化層有較深的載子捕捉位置有好的關連性。

According to establishing the newest evolutionary trend for the gate nano scale of MOSFETs from ITRS PIDS Meeting in 2008 year, the nano microelectronic devices applied high performance and low power function circuits must put off three or five process generation because the novel gate materials can be unable to sustain the criterion of the least gate leakage current tolerably previous works. A process-compatible CF4 plasma treatment technique for fabricating fluorinated silicate oxide (FSG) as a passivation layer of n-MOSFETs is demonstrated in this work. Fluorine was effectively diffused into the high-k gate dielectric and the interface between channel and gate dielectric during sintering step. Experimental results reveal that remarkably improved device performance and reliability can be achieved with appropriate CF4 gas introduced. Thus, the electrical characteristics improvement exhibits driving current enhanced due to mobility improvement, good subthreshold slope, low gate leakage current, obviously reduced GIDL current and so on. In addition, the fluorinated P.L. ( the abbreviation of passivative layer) also improves the device reliability with respect to positive bias temperature stress (PBTS) and hot-carrier stress (HCS). We observe that less threshold voltage shift, less generated bulk trap density and interface state density shift during voltage stressing, which suppressing the instability characteristics due to device damage. For n-MOSFET devices with TEOS P.L. or FSG P.L., compared PBS and HCS, we find that the HCS phenomenon on reliability degradation is more serious than PBS. It shows the improvement of electrical characteristics and good stability as well as reliability in devices for FSG P.L. as a result of the fluorine atoms incorporated into high-k gate dielectric and the interface between gate dielectric and channel, which not only reducing interface dangling bonds and lower generation rates of interface states, but also effectively lowering carrier trapping in high-k dielectric further. Finally, the relaxation behavior after hot carrier stressing test could separate cold carrier from hot carrier, which the effect of total threshold voltage shift coming of cold and hot carriers. The cold carrier contribution is shown to be reversible while hot carrier trapping induces permanent damage of the dielectric. It is clearly noted for devices of fluorinated passivation layer that less carriers are captured in high-k bulk dielectric and interface (stress cycle) but less captured carriers take place de-trapping behavior due to higher de-trapping barrier height (relaxation cycle). As observed above, it shows a good correlation between F-P transport mechanism and de-trapping behavior that the position of carriers trapping for FSG P.L. are deeper than that for TEOS P.L..