提昇多指狀靜電放電保護元件導通均勻度之設計

Abstract

隨著製程不斷的演進，積體電路元件的規模也從微米縮小至奈米，同時也伴隨著閘極氧化層的厚度變得越來越薄。此外，為了增加互補式金屬氧化層半導體中積體電路的操作速度，金屬矽化層已是一道非常重要且必備的光罩。而上述這些對積體電路的效能是正面的助益，但是卻對靜電放電(Electrostatic Discharge, ESD)防護耐受度造成嚴重的下降。為了能維持足夠的靜電放電耐受度，在一般積體電路上，靜電放電防護電路是需要加入的。 在靜電放電路徑產生時，為了能讓靜電放電保護元件承受更大的電流，一般會增加 元件的通道寬度，而形成一種多指狀的結構。而在NMOS的導通機制中，會有一個電壓突然跳回的點(snapback)，這是由於NMOS閘極下有一個寄生的橫向npn雙載子接面電晶體，其電流增益(β gain)很大的緣故。而這則會造成多指結構NMOS的不均勻導通，使電流集中在先導通的指頭上，因而容易造成燒灼，降低了靜電放電的耐受度。因此，在不斷的增加通道寬度，加大面積下，靜電放電保護能力並不會隨著線性提升。而在我的論文中則會對此不均勻導通的問題提出方法來解決，提出的設計將不需要任何複雜的拉線技巧，也不用外加觸發電路，只需要在元件佈局上做變化即可。第一部份提出的是折彎N-Well穩定電阻(bending N-Well ballast resistance)技術，而套用在閘極接地的NMOS。這設計的概念是用一折彎N-Well電阻而避開使用金屬矽化層阻隔(silicide blocked mask)這層光罩。這設計成功在55奈米的CMOS製程下實現，相較於傳統的N-Well穩定電阻技術，也在較好的靜電放電耐受度下得到驗証。而第二部份提出的是基板隔離(isolated-body)的技巧。因為傳統使金屬矽化層阻隔的多指結構NMOS仍有不均勻導通的問題，因此在本論文中對其來做改良。在此設計下，他的基板能看到一樣的基板電阻(substrate resistance)，而有均勻導通的效果。而此設計也在55奈米的CMOS製程下實現了。和傳統的多指結構NMOS以及使用插入源極端短路基底接觸點(source butting substrate contact)的技術相較起來，本論文新提出的基板隔離技巧在實驗結果中能有更小的導通電流，也有更好的靜電放電耐受度。

While the process evolution from microscale to nanoscale, the device size is continually scaled down, and so does the gate oxide thickness. The silicide process now is a common procedure to improve the operating speed of CMOS ICs. These are positive to the performance of IC chips, but negative to electrostatic discharge (ESD) robustness. To sustain a required ESD robustness in CMOS ICs, the chip should contain ESD protection circuits inside. In order to discharge enough ESD current as the ESD event occurs, the MOSFET in ESD protection circuit should be drawn in multi-finger layout structure to maintain enough channel width for discharging ESD current. But there is a snapback breakdown phenomenon due to NMOS parasitic lateral bipolar beta gain. This will cause multi-finger non-uniform turn-on issue, degrade the ESD robustness. As a result, the ESD robustness can’t increase effectively by increasing the channel width and area of device. The purpose of this thesis is to solve the non-uniform turn-on phenomenon of multi-finger NMOS. The proposed designs use only layout technique to fulfill without external triggering circuit and increase of layout area. The first proposal is bending N-Well ballast resistance technique applied to gate-grounded NMOS (GGNMOS). The design concept is using N-Well resistance without silicide blocked mask, and it has been successfully verified in a 55-nm CMOS process, and the ESD robustness of bending N-Well ballast resistance GGNMOS could be improve than that of traditional N-Well ballast resistance GGNMOS. The second proposal is the isolated-body technique. Because there is still the non-uniform turn-on issue on traditional silicide blocked multi-finger NMOS, isolated-body is a design to achieve substrate resistance equalization of every finger, it has been realized in a 55-nm CMOS process. The experimental results show that isolated-body structure has smaller trigger current than traditional multi-finger NMOS and inner pickup structure NMOS. The HBM ESD level could also be improved through this design.