利用一倍供應電壓元件實現兩倍供應電壓共容輸入輸出緩衝器設計

Abstract

隨著互補式金氧半導體(Complementary Metal-Oxide-Semiconductor, CMOS)積體電路製程技術的演進，電晶體閘極氧化層(gate-oxide)的厚度越來越薄，其所能承受的最大跨壓，包括閘極-源極電壓(Vgs)和閘極-汲極電壓(Vgd)也跟著變小。為增快電路的工作速度，以及降低能源的消耗，近來的積體電路設計所使用之工作電壓也跟著降低。然而較早的CMOS製成技術所設計的電路，使用相對於先進製程所能忍受的較大工作電壓。混合電壓輸出入緩衝器 (mixed-voltage I/O buffer)作為不同電壓之傳輸介面，如何避免閘極氧化層過壓 (gate-oxide overstress)以提高積體電路的使用壽命，是一項重要的課題。此外電路的操作速度越來越快，如何降低接地彈跳(ground bounce)的影響，也是一個特別的挑戰。更進一步地，為確保訊號的完整性和維持電路速度上的表現，輸出入緩衝器必須使電壓迴轉率(slew rate)的變異量越小越好。 在本篇論文當中，提出了一個使用一倍供應電壓元件的一個二倍供應電壓共容輸入輸出緩衝器，且驗證於0.18□m CMOS製程技術，伴隨動態源極輸出技術 (dynamic source output technique)和新閘極控制電路(new gate-controlled circuit)，其可以傳送及接收二倍供應電壓之訊號且不會發生閘極氧化層過壓的問題。此新提出之二倍供應電壓共容輸入輸出緩衝器可在不同的CMOS製程下實現，以滿足不同的混合電壓介面之應用。 在論文的後半，將此新提出之二倍供應電壓共容輸入輸出緩衝器結合電壓迴轉率控制(slew-rate control)電路，以降低接地彈跳的影響。此外，此新提出之二倍供應電壓共容輸入輸出緩衝器也結合了製程、電壓及溫度補償(process, voltage, and temperature compensation)電路，使電壓迴轉率(slew rate)的大小在不同的環境下，仍能維持在一定的範圍以內。

With the advance of complementary metal-oxide-semiconductor technology, the gate-oxide of the transistor becomes thinner and the maximum voltage across the gate-oxide including gate-source voltage (Vgs), gate-drain voltage (Vgd) of the MOS transistor has decreased drastically. In order to increase the operating speed and decrease the power consumption, the supply voltage of recent design of an integrated circuit has been decreased. However, the earlier defined standards or interface protocols of CMOS ICs use the supply voltage higher than the advanced CMOS process. The mixed-voltage I/O buffer acts the interface of different voltage levels, so the avoidance of gate-oxide overstress to extend the circuit’s life time is an important issue in nanoscale technology. In addition, the ground bounce effects get worse with increasing operating speed. It also presents special challenges for I/O designers. Furthermore, to ensure the validity of signals and maintain the operating speed, it is another important issue to keep the output slew-rate as constant as possible. In this thesis, a new 2xVDD-tolerant I/O buffer realized with only 1xVDD devices has been proposed and verified in a 0.18-μm CMOS process. With the dynamic source output technique and the new gate-controlled circuit, the new proposed I/O buffer can transmit and receive the signals with the voltage swing twice as high as the normal power supply voltage (VDD) without suffering gate-oxide reliability problem. The proposed 2xVDD-tolerant I/O circuit solution can be implemented in different nanoscale CMOS processes to meet the mixed-voltage interface applications in microelectronic systems. Furthermore, to reduce the ground bounce effects, the new 2xVDD-tolerant I/O buffer is combined with the slew-rate control circuit. In addition, the new 2xVDD-tolerant I/O buffer is also combined with PVT compensation circuit to make the output slew rate as constant as possible.