标题: 高效能之NAND型快闪记忆体控制器
HIGH-PERFORMANCE NAND FLASH CONTROLLER
作者: 高于翔
Kao, Yu-Hsiang
黄俊达
Huang, Juinn-Dar
电子研究所
关键字: 快闪记忆体;控制器;NAND flash;controller
公开日期: 2009
摘要: NAND型快闪记忆体之小面积及低功耗使之成为现今最重要的非挥发性记忆元件之一。它快速的读写时间让其非常适合成为次世代之大量储存媒介。然而,NAND型快闪记忆体的输出入介面之工作频率限制了资料传输的频宽。为了在此频宽限制下得到更高的效能,新世代的NAND型快闪记忆体元件提供交错以及双面运行之指令。因此NAND型快闪记忆体控制器也必须拥有支援这些先进指令集之能力以使整体之系统效能提升。
在本篇论文中,我们提出一个高效能之NAND型快闪记忆体控制器。它主要使用了两项技巧,包括平行化指令处理及使用双面指令之定址模式。藉由这些技巧,我们可以尽可能地将指令间的平行度最大化并降低单一指令平均之执行时间以得到较好的效能。实验结果显示,我们所提出的快闪记忆体控制器相较于一般基本功能之控制器在各种读写之效能均可提升达18%以上。
NAND flash memory is one of the most important components in non-volatile storage media because of its small size and low power consumption. Its fast erase and program time has made NAND flash very suitable for the new generation mass-storage device. However, the I/O interface frequency of NAND flash has limited the bandwidth of data transfer. In order to achieve higher performance under this bandwidth limitation, NAND flash device provides interleaved and two-plane command sets. Therefore, NAND flash controller must have the ability to enhance the related functionality to improve the overall system performance.
In this thesis, we propose a high-performance NAND flash controller by utilizing the two techniques, including out-of-order execution with multi-die commands and the two-plane addressing mode. By these techniques, we can maximize the commands being executed in parallel and shorten the average execution time per instruction to achieve higher data access performance. The experimental results show that the proposed NAND flash controller can improve the data access performance for both read and program for at least 18% compared to a basic NAND flash controller.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079611630
http://hdl.handle.net/11536/41755
显示于类别:Thesis


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