全數位寬電壓範圍寬頻率範圍延遲鎖定迴路時脈產生器設計

Abstract

本論文提出一個全數位式、寬電壓範圍、寬頻率範圍延遲鎖定迴路時脈產生器。藉由高穩健性的電路技巧使用，本電路能正常操作在寬電壓範圍。此外，為了達到快速鎖定，以及增加操作頻率範圍並且同時避免多諧鎖定，提出了一個可變性連續近似暫存器搜尋演算法，其特點在於結合頻率估計選擇器，提供不同的初始延遲時間已達到上述的功能。一個連續近似暫存控制器應用在多相位延遲鎖定迴路於UMC 90nm CMOS技術，模擬結果顯示，在1.0V工作電壓下，可操作頻率為250MHz到1.25GHz ；在0.3V工作電壓下操作頻率為13MHz到75MHz。 一個125MHz到2.5GHz全數位延遲鎖定迴路時脈產生器實現在UMC 90nm CMOS技術。為了達到動態調整頻率或電壓來減少功率消耗，一個穩健且可程式化的頻率倍乘器被提出。此外，一個新型的漏電流減少數位控制延遲元件被提出，根據模擬顯示，可減少10%漏電流且不減緩電路的操作頻率。本時脈產生器其最大消耗的總功率為0.71毫瓦當操作在500MHz且產生250MHz 、500MHz 、1GHz及2GHz等四種不同頻率。本論文提出的延遲鎖定迴路可穩定地使用在各種嵌入式記憶體應用及可攜式產品中。

An all-digital wide power supply range wide frequency range DLL-based clock generator is proposed in this thesis. In order to operate in wide power supply range, the robust circuit methodology is used in this design. Besides, an adaptive successive approximation register-controlled (ASAR) search algorithm is proposed to extend the locking range and avoid harmonic lock at the same time. An ASAR based controlled is adopted in multiphase DLL implemented in UMC 90nm CMOS technology. The simulation results show that, the operating frequency is from 250MHz to 1.25GHz at 1.0V, and 13MHz to 75MHz at 0.3V, respectively. A 125MHz-2.5GHz all-digital DLL-based clock generator has been designed in UMC 90nm CMOS technology. In order to achieve dynamic frequency/voltage scaling application, the robust and programmable frequency multiplier is proposed. Besides, the novel leakage-reduced delay unit is proposed to take advantages of mitigating 10% leakage current, insensitive to PVT variations, and not degrading operating frequency of circuit. The simulation results show the proposed DLL-based clock generator exhibits maximum power dissipation 0.71mW when operate in 500MHz, generating 250MHz, 500MHz, 1GHz, and 2GHz four different frequency at the same time. The presented DLL clock generator can be robustly used in embedded memory applications and portable device.