低功耗壓控振盪器設計與順向基極偏壓之應用

Abstract

本論文利用RF CMOS製程設計了應用於無線通訊接收端之低功耗壓控振盪器。現代通訊系統之中，壓控振盪器是不可或缺的元件，加上無線網路和可攜式無線通訊的普及應用，設計低功耗及低相位雜訊的振盪器是一個關鍵性而值得研究探討的題目。 內容在於使用金氧半互補式製程，設計並實現微波振盪器，主要分成三個部分，第一部分為介紹相位雜訊的產生，以及LC振盪器的原理。第二部分為利用共面波導(CPS)取代普通電感，並使用floating metal strips減少基板的耗損性，提升品質因子，做為共振器且其對稱性可以有效減少布局所需要的面積。以及利用對電晶體基極端加順向偏壓來降低臨界電壓進一步降低供應電壓來達成低功耗電路設計。此壓控振盪器製作採用台積電0.18微米 RF CMOS 製程來實現，然而量測結果顯示不如模擬之預期，在供應電壓1.5伏特操作下，其功率消耗為45毫瓦，可調頻段(tuning range) 在改變電壓(Vtune) -1.5 ~1.5伏特範圍內為18 ~19.3 GHz 相當於 7%之可調範圍，輸出功率介於-16.5~-22.7 dBm，相位雜訊於1MHz offset frequency之下為-85.5 ~ -100.9 dBc/Hz。 第三部分使用台積電0.18微米 RF CMOS 製程來實現一個使用順向基極偏壓技術的壓控振盪器。本設計利用對電晶體基極端加順向偏壓來降低臨界電壓進一步降低供應電壓來達成低功耗電路設計。根據ADS 模擬其設計目標為操作電壓0.7V可達功耗小至3.2毫瓦。而量測結果顯示在操作電壓為0.7V條件下，其功耗為3.36 毫瓦。其可調頻段在改變電壓Vtune = 0~1.8伏特為17.9 ~20 GHz，即可調頻段為 10.8%。於此操作條件下，輸出功率介於-7.67~ -4.3 dBm，相位雜訊在1MHz offset frequency下為 –88 ~ -91.23 dBc/Hz。

In this thesis, low-power Voltage-controlled oscillator (VCO) design and fabrication have been realized using 0.18 □m 1.8V RF CMOS technology for applications in wireless receivers. The VCO is indispensable in modern communication systems. The rapidly increasing applications in portable and universal wireless systems drive our research effort in this thesis to investigate VCO design techniques for low power consumption and low phase noise. The objective is aimed at sub-5mW and low phase noise VCOs, which are applicable to the spectrum domain of 18 ~ 24 GHz. The thesis consists of three parts. The first part introduces the fundamental theory of phase noise and principle of LC-tank VCOs. In the second part, the first VCOs chip was designed using coplanar stripline (CPS) for replacing spiral inductors and floating metals for ground shielding and reducing substrate loss. The former one, i.e. adoption of CPS can improve the quality factor and reduce the chip area due to better layout symmetry. Furthermore, forward body biases scheme was applied to the MOSFET for reducing the threshold voltage (VT) and then lowering the supply voltage VDD. This first VCO chip consumes 35 mW at the core oscillator and total power of around 40 mW from 1.5V. The tuning range achievable from –1.5V to 1.5V is 18 ~ 19.3 GHz, that is around 7% of the center frequency. The measured phase noise is in the range of -85.5~-100.9 dBc/Hz at 1 MHz offset and the deliverable output power is -16.5~ -22.7 dBm. In the third part, the second VCO chip was designed using forward body bias scheme for low voltage and lower power operation. The supply voltage can be pushed to as low as 0.7V and the dc power consumption measured from the whole chip is 3.36mW. The tuning range achievable from 0V to 1.8V is 17.9 ~ 20 GHz, that is around 11% of the center frequency. The measured phase noise corresponding to tuning range is -88~-91.23 dBc/Hz at 1 MHz offset and the deliverable output power is –88 ~ -91.23 dBc/Hz.