使用0.18μm 互補式金氧半製程設計具有過沖偵測之6Gb/s 可適性等化器

Abstract

本論文提出並探討能應用在可適性等化器架構中的過沖偵測機制。此機制可避免電路需使用雙相限制器和整流器，使電路達到高速低功率的目的。本論文提出並且實現了兩個電路設計，皆由CMOS 0.18"μ" m製程製作而成，使用的電源均為1.8V。兩項設計實現了相同的規格，藉此比較和驗證兩項創新電路設計上的優勢。第一個電路將過沖偵測機制應用在傳統的閉迴路的等化器系統中，且能達到6Gbs/s 的資料傳輸率，最長能補償到40英吋的FR4通道。量測結果顯示電路具有非常好的時脈抖動表現，且僅有40mW的功率消耗。第二個電路設計提出多級且擁有功率管理功能性的等化器架構，且亦能達到6Gb/s的資料傳輸率。此電路能在處理訊號衰減量較小的情況時，能節省大量的功率消耗。量測結果顯示電路能有良好的時脈抖動表現且在補償12英忖的FR4通道情形下僅消耗15.3mW的功率，而在較長的33英吋情況下消耗43mW，相當於62%的功率節省率。

This thesis proposes a new overshoot detection mechanism for application in adaptive equalizers. The detection method obviates the need for slicers or rectifiers, achieving a high-speed, low-power equalizer design. Two equalizer circuit designs with similar specifications are proposed and implemented in this thesis to emphasize the advantages of each proposed technique. Both works are fabricated in 0.18"μ" m technology, and are both capable of operating at 6Gb/s. The first work incorporates the overshoot detection mechanism to adjust the boosting in a traditional closed-loop equalizer. The circuit is capable of adapting to FR4 traces for lengths up to 40 inches. The measurement results show that the equalizer achieves excellent eye performance while only consuming 40mW from a 1.8-V supply. The second work proposes a novel multi-stage equalizer with power management capability. The equalizer saves significant amounts of power when equalizing signals with lower losses. The measurement results show that the equalizer produces good eye performance while consuming only 15.3mW for equalization of a 12inch FR4 trace and 43mW for a 33inch FR4 trace from a 1.8-V supply, which is equal to a 62% savings in power dissipation.