具差動功率攻擊防禦之先進加密標準核心設計與安全性分析

Abstract

先進加密標準(AES)目前已是最為廣泛使用的對稱性加密演算法，其最主要的原因在於高安全性、高效能及以實現低複雜度。舉凡無線通訊系統、資料儲存系統、智慧型晶片卡以及銀行系統等等都大量地採用AES為加密標準。現有文獻已有不少AES硬體實作的探討、但是這些文獻往往未將低成本同時具備高效能的設計技巧考量進去。因此在本論文我們先探討在不同需求的應用上(包含超高速應用以及超低成本應用)的架構設計。綜合以上設計概念，我們提出了一個高效益的AES硬體架構。而此硬體架構可以支援標準所訂的三種金鑰長度以及加/解密能力。整體的架構主要是由一高度化簡之即時金鑰產開元件以及一高度整合之加/解密資料處理元件所組成。即時金鑰產開元件共用了不同金鑰長度所需要的硬體資源來大幅降低成本；而整合資料處理元件則是共用了加密與解密所需要的資料。在透過矽晶片實作以及量測後，同時透過矽晶片之實作與量測，驗證所提之方法之分析與效益。 然而，AES演算法的硬體實作存在著一個相當大的安全性風險：差動功率攻擊。此種攻擊法可以很有效率地破解出AES晶片運算時所使用之金鑰。在本論文中，我們也進一步探討防禦此種攻擊法的方法。透過一基於數位振盪器以及亂數產生品的防禦電路，我們提出了一低成本且高效能的AES晶片來抵抗差動功率攻擊。相較於現有之文獻，我們所提出來的方法無論是在額外成本支出或是效能降低比例都能大幅的改善。而透過矽晶片的實作與量測，我們所提出的抗差動功率攻擊的AES晶片可以達到最快255MHz的操作頻率，而在此操作頻率下的效能為2.97Gb/s。同時防禦電路所需要的額外成本支出僅為原本AES電路的6.2%。在安全度分析下，measurement to disclosure (MTD)可以從數千大幅增加至107，至少增加了三個數量級以上的安全度。

The AES algorithm approved in 2001 has become the most popular symmetric-key encryption algorithm because of its high security, high performance, and low complexity. The AES algorithm is widely adopted in numerous applications such as wireless communications, storage devices, smart cards, or banking systems. Several implementations have been published but few of them considered the hardware cost and the throughput as a whole. In this dissertation, we first investigate architectures for high throughput and low cost applications. At last a cost efficient AES architecture, which is capable of both encryption and decryption with three different key lengths, is presented for high speed mobile applications. The overall hardware cost is optimized by a very compact on-the-fly key expansion unit and a highly integrated encryption/decryption data-path. The compact on-the-fly key expansion unit is achieved by sharing key scheduling processes of different key lengths. The integrated data-path shares hardware resources used in encryption and decryption. After manufactured in 90nm CMOS technology, the area of the chip is 15,577 equivalent gates with throughput up to 1.69 Gb/s operating at 131.8 MHz. However, the hardware implementation of the AES algorithm is still vulnerable to side-channel attacks. The differential power analysis (DPA) attack is an efficient and low cost method to disclose the secret key of the AES chip. In this dissertation, a low cost AES crypto core with resistance to the DPA attack is presented by exploiting a DPA countermeasure circuit based on digital ring oscillators and an on-chip random number generator (RNG). Two architectures with pseudo random and digital random number generator are presented. Compared with previous works that counteract the DPA attack by using data masking circuits or equalizing the power consumption, our proposed DPA countermeasure circuit can significantly reduce the area overhead without throughput degradation. The DPA resistant AES engines are fabricated in UMC 90 nm CMOS technology. For the pseudo random based architecture, the AES chip can achieve 2.76 Gb/s throughput at operating frequency of 237 MHz. The area overhead is minimized to 10.2%. For the digital random based architecture, the AES chip can achieve 2.97 Gb/s throughput at operating frequency of 255 MHz. The area overhead is slightly improved from 10.2% to 6.2% by resource sharing between the DPA countermeasure circuit and the random number generator. The digital random based architecture further resolves the “reset” problem, which may induce a security issue for the PRNG based architecture. The measurement to disclosure (MTD) of both AES engines is increased from several thousands to more than 107 measurements, indicating the security level is enhanced by at least three orders of magnitude.